opensbi.git/platform/generic/allwinner, branch v1.5

platform: generic: allwinner: Optimize current hart scratch access

2024-04-05T12:04:25Z

The address of the local scratch area is stored in each hart's mscratch CSR. It is more efficient to read the CSR than to compute the address from the hart ID. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions

2024-03-20T05:35:13Z

All T-Head CSRs are already defined in thead/c9xx_encoding.h. Let's reuse the values from there instead of redefining them with a slightly different name. Signed-off-by: Christoph Müllner Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx pmu

2023-11-14T16:23:45Z

Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: move to thead c9xx header to vendor specific postion

2023-11-14T16:23:42Z

The CSR encoding for t-head c9xx cores is shared across all the platforms with these cores. So move header thead_c9xx.h to the thead subdir. Signed-off-by: Inochi Amaoto Acked-by: Guo Ren Reviewed-by: Anup Patel

platform: generic: allwinner: fix OF process for T-HEAD c9xx pmu

2023-09-10T05:34:59Z

T-HEAD c9xx pmu needs to clear OV bits of MCOUNTEROF in any condition to avoid unnecessary OF interrupts. In addition, the S-mode SCOUNTEROF only have OF bit set when the related bits of MCOUNTERWEN is set, so also configure MCOUNTERWEN to allow kernel to access valid SCOUNTEROF. Signed-off-by: Haijiao Liu Co-authored-by: Inochi Amaoto Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel Tested-by: Samuel Holland

platform: generic: allwinner: correct mhpmevent count

2023-08-22T07:56:05Z

Only the CSR mhpmevent 3-9,13-17 of D1 have valid function, so change the mhpm_mask to a valid value to avoid invalid usage. Due to the openc906 pmu code https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic/allwinner: Fix sun20i-d1.c header dependency

2023-02-27T04:30:15Z

The code calls various macros from riscv_asm.h and sbi_scratch.h which are not directly included. Fix such dependency. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: generic: allwinner: Advertise nonretentive suspend

2023-01-24T12:00:21Z

Add D1's nonretentive suspend state to the devicetree so S-mode software knows about it and can use it. Latency and power measurements were taken on an Allwinner Nezha board: - Entry latency was measured from the beginning of sbi_ecall_handler() to before the call to wfi() in sun20i_d1_hart_suspend(). - Exit latency was measured from the beginning of sbi_init() to before the call to sbi_hart_switch_mode() in init_warmboot(). - There was a 17.5 mW benefit from non-retentive suspend compared to WFI, with a 170 mW cost during the 107 us entry/exit period. This provides a break-even point around 1040 us. Residency includes entry latency, so round this up to 1100 us. - The hardware power sequence latency (after the WFI) is assumed to be negligible, so set the wakeup latency to the exit latency. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

platform: generic: allwinner: Fix PLIC array bounds

2023-01-13T12:09:42Z

The two referenced commits passed incorrect bounds to the PLIC save/ restore functions, causing out-of-bounds memory access. The functions expect "num" to be the 1-based number of interrupt sources, equivalent to the "riscv,ndev" devicetree property. Thus, "num" must be strictly smaller than the 0-based size of the array storing the register values. However, the referenced commits incorrectly passed in the unmodified size of the array as "num". Fix this by reducing PLIC_SOURCES (matching "riscv,ndev" on this platform), while keeping the same array sizes. Addresses-Coverity-ID: 1530251 ("Out-of-bounds access") Addresses-Coverity-ID: 1530252 ("Out-of-bounds access") Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers") Fixes: 9a2eeb4aaeac ("lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers") Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30Z

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel