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<title>opensbi.git/platform/generic/allwinner, branch v1.6</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/platform/generic/allwinner?h=v1.6</id>
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<updated>2024-12-06T03:56:35Z</updated>
<entry>
<title>lib: sbi: Add optional resume address to hart suspend</title>
<updated>2024-12-06T03:56:35Z</updated>
<author>
<name>Subrahmanya Lingappa</name>
<email>slingappa@ventanamicro.com</email>
</author>
<published>2024-08-06T05:08:46Z</published>
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<id>urn:sha1:fdd72635368beb5f9c85533b92abb31adee20406</id>
<content type='text'>
Add an optional resume address to the platform specific hart suspend call.

Signed-off-by: Subrahmanya Lingappa &lt;slingappa@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Move per-hart data from fdt_plic to plic</title>
<updated>2024-11-28T06:05:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:06Z</published>
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<id>urn:sha1:56fddce83f163e5e90ea82bf78a8df3d990b0572</id>
<content type='text'>
The per-hart PLIC pointer is not really specific to FDT platforms. Move
it into the main driver and drop the extra wrapper functions.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Common PM save/restore</title>
<updated>2024-11-28T05:58:38Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:05Z</published>
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<id>urn:sha1:c6c22f00f457264560ca05414e9f9e0c5c3438db</id>
<content type='text'>
Move the PLIC save/restore functions inside the driver, so they can be
reused on any platform that needs them. The memory needed to store the
PLIC context is also allocated by the driver. The PM data cannot be
completely encapsulated, as some platforms (including Allwinner D1) need
to program the IRQ enable status to a sideband interrupt controller for
wakeup capability.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Pass FDT to early/final_init overrides</title>
<updated>2024-08-24T07:32:54Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-31T04:58:54Z</published>
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<id>urn:sha1:6e5db7b09c6c25be59900a3470923727a4e14033</id>
<content type='text'>
Several of these override functions access the FDT blob. Explicitly
indicate which callbacks are allowed to modify the FDT blob by passing
the parameter as a possibly-const pointer. This also reduces code size
by deduplicating the call to fdt_get_address().

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: allwinner: Optimize current hart scratch access</title>
<updated>2024-04-05T12:04:25Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-03-18T14:49:29Z</published>
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<id>urn:sha1:f5375bc15e9f3e577dfc24f9095a3e37246a3fa3</id>
<content type='text'>
The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions</title>
<updated>2024-03-20T05:35:13Z</updated>
<author>
<name>Christoph Müllner</name>
<email>christoph.muellner@vrull.eu</email>
</author>
<published>2024-03-19T09:26:42Z</published>
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<id>urn:sha1:5186da687debaab5c4a81ec351e56d145d88c79c</id>
<content type='text'>
All T-Head CSRs are already defined in thead/c9xx_encoding.h.
Let's reuse the values from there instead of redefining them with
a slightly different name.

Signed-off-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: separate implement of T-HEAD c9xx pmu</title>
<updated>2023-11-14T16:23:45Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-07T03:06:29Z</published>
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<id>urn:sha1:8e941e7fe3b8244107832b931980006bf9b0dc55</id>
<content type='text'>
Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: move to thead c9xx header to vendor specific postion</title>
<updated>2023-11-14T16:23:42Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-07T03:06:28Z</published>
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<id>urn:sha1:c1a69874476810aa47bb1ca8bbe7697f855dba5f</id>
<content type='text'>
The CSR encoding for t-head c9xx cores is shared across all the
platforms with these cores. So move header thead_c9xx.h to the
thead subdir.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Acked-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: allwinner: fix OF process for T-HEAD c9xx pmu</title>
<updated>2023-09-10T05:34:59Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-08-15T09:40:32Z</published>
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<id>urn:sha1:c9a296d0edc9cb64638c026949ef091d7d9e01e9</id>
<content type='text'>
T-HEAD c9xx pmu needs to clear OV bits of MCOUNTEROF in any condition
to avoid unnecessary OF interrupts.

In addition, the S-mode SCOUNTEROF only have OF bit set when the related
bits of MCOUNTERWEN is set, so also configure MCOUNTERWEN to allow kernel
to access valid SCOUNTEROF.

Signed-off-by: Haijiao Liu &lt;haijiao.liu@sophgo.com&gt;
Co-authored-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: allwinner: correct mhpmevent count</title>
<updated>2023-08-22T07:56:05Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-08-11T00:13:01Z</published>
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<id>urn:sha1:e7e73aa532fa5813f457b9b09899413f41885d37</id>
<content type='text'>
Only the CSR mhpmevent 3-9,13-17 of D1 have valid function, so change
the mhpm_mask to a valid value to avoid invalid usage.

Due to the openc906 pmu code
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel  &lt;anup@brainfault.org&gt;
</content>
</entry>
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