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<title>opensbi.git/platform/generic/andes/ae350.c, branch master</title>
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<updated>2026-02-11T06:44:04Z</updated>
<entry>
<title>lib: utils/suspend: add Andes ATCSMU suspend driver</title>
<updated>2026-02-11T06:44:04Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2025-12-29T07:19:14Z</published>
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<id>urn:sha1:b27ecec76b8acfece9c28078d02cbc6bc762135c</id>
<content type='text'>
Implement a system-wide suspend driver for the Andes AE350 platform.
This driver supports Andes-specific deep sleep (suspend to RAM) and
light sleep (suspend to standby) functionalities via the ATCSMU.

The major differences between deep sleep and light sleep are:

- Power Domain and Resume Path: Deep sleep powers down the core domain.
  Consequently, harts waking from deep sleep resume from the reset
  vector. Light sleep utilizes clock gating to the core domain; harts
  maintain state and resume execution at the instruction immediately
  following the WFI instruction.

- Primary Hart Wakeup: In both modes, the primary hart is woken by
  UART or RTC alarm interrupts. In deep sleep, the primary hart is
  additionally responsible for re-enabling the Last Level Cache (LLC)
  and restoring Andes-specific CSRs.

- Secondary Hart Wakeup: In light sleep, secondary harts are woken
  by an IPI sent from the primary hart. In deep sleep, they are
  woken by an ATCSMU hardware wake-up command. Furthermore,
  secondary harts must restore Andes-specific CSRs when returning
  from deep sleep.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic/andes: add CSR save and restore functions for AE350 platform</title>
<updated>2026-02-11T06:34:01Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2025-12-29T07:19:11Z</published>
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<id>urn:sha1:85bff9cc163e05130899264eb6e963fc582de117</id>
<content type='text'>
Implement a save and restore mechanism for Andes-specific CSRs to support
hardware power-saving modes, such as CPU hotplug or suspend to RAM.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/hsm: factor out ATCSMU code into an HSM driver</title>
<updated>2026-02-11T06:33:50Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2025-12-29T07:19:10Z</published>
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<id>urn:sha1:9ffacc8ae1ca07ed36d57f887d62a65ae7a44223</id>
<content type='text'>
Refactor ATCSMU (System Management Unit) support by moving it from a
system utility into a dedicated FDT-based HSM driver.

Key changes include:

- Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver
- Moving hart start and stop operations on AE350 platform into the new
  HSM driver
- Converting the assembly-based functions in sleep.S to C code for the
  readability
- Updating the ATCWDT200 driver

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devices</title>
<updated>2025-10-28T05:58:01Z</updated>
<author>
<name>Nick Hu</name>
<email>nick.hu@sifive.com</email>
</author>
<published>2025-10-20T06:34:10Z</published>
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<id>urn:sha1:94f0f8465622e121d65f70d2cce6101d8d716a80</id>
<content type='text'>
A platform may contain multiple IPI devices. In certain use cases,
such as power management, it may be necessary to send an IPI through a
specific device to wake up a CPU. For example, if an IMSIC is powered
down and reset, the core cannot receive IPIs from it, so the wake-up must
instead be triggered through the CLINT.

Suggested-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Remove platform override hooks</title>
<updated>2025-04-23T07:02:51Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-03-25T23:43:30Z</published>
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<id>urn:sha1:b80ded7756c233ebe9536b77823c51e916e43ffa</id>
<content type='text'>
Now that all of the overrides are modifying generic_platform_ops
directly, remove the unused hooks and forwarding functions. The
remaining members of struct platform_override match struct fdt_driver,
so use that type instead. This allows a future commit to reuse the
fdt_driver-based init function.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Modify platform ops instead of using hooks</title>
<updated>2025-04-23T07:02:51Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-03-25T23:43:29Z</published>
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<id>urn:sha1:b353af63e2223409698a5afce7a6413204a499dd</id>
<content type='text'>
Switch all existing platform overrides to use the helper pattern instead
of the platform hooks. After this commit, only the .match_table and
.init members of struct platform_override are used.

There are two minor behavioral differences:
 - For Allwinner D1, fdt_add_cpu_idle_states() is now called before the
   body of generic_final_init(). This should have no functional impact.
 - For StarFive JH7110, if the /chosen/starfive,boot-hart-id property is
   missing, the code now falls back to using generic_coldboot_harts,
   instead of accepting any hart.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250325234342.711447-7-samuel.holland@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Update sbi_{entry,init}_count() to take a hart index</title>
<updated>2024-09-26T10:59:27Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-08-30T15:49:15Z</published>
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<id>urn:sha1:3962be84d4e3997beaf739475d9d504d274517d8</id>
<content type='text'>
All callers already have the hartindex available, so this removes a
hartid to hartindex conversion.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Pass FDT to early/final_init overrides</title>
<updated>2024-08-24T07:32:54Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-31T04:58:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=6e5db7b09c6c25be59900a3470923727a4e14033'/>
<id>urn:sha1:6e5db7b09c6c25be59900a3470923727a4e14033</id>
<content type='text'>
Several of these override functions access the FDT blob. Explicitly
indicate which callbacks are allowed to modify the FDT blob by passing
the parameter as a possibly-const pointer. This also reduces code size
by deduplicating the call to fdt_get_address().

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: andes: add Andes SBI call to probe Andes PMA feature</title>
<updated>2024-08-23T08:35:39Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-07-23T07:57:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=4a72abb5f490c01a5a4dd24930ccae9c42d15c74'/>
<id>urn:sha1:4a72abb5f490c01a5a4dd24930ccae9c42d15c74</id>
<content type='text'>
Add a new Andes SBI call to check whether PPMA is supported by hardware
or not.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: andes: Change all occurrences of andes45 to andes</title>
<updated>2024-05-09T12:27:51Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-04-19T03:58:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=2b93ce0954d594a1c4919f02187bbf7177ed412d'/>
<id>urn:sha1:2b93ce0954d594a1c4919f02187bbf7177ed412d</id>
<content type='text'>
To make the framework suit all Andes CPUs, change all occurrences of
andes45 to andes.

In addition, we fix some coding style problems and remove an unused
macro in andes.h.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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