opensbi.git/platform/generic/andes, branch master

platform: generic: Optimize extensions_init() to parse ISA extensions once

2026-06-12T10:38:29Z

Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/suspend: add Andes ATCSMU suspend driver

2026-02-11T06:44:04Z

Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel

platform: generic/andes: add CSR save and restore functions for AE350 platform

2026-02-11T06:34:01Z

Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel

lib: utils/hsm: factor out ATCSMU code into an HSM driver

2026-02-11T06:33:50Z

Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel

lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devices

2025-10-28T05:58:01Z

A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: Allow custom CSRs in csr_read_num() and csr_write_num()

2025-10-21T14:04:09Z

Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

platform: generic: Add Andes QiLai SoC support

2025-09-30T12:18:11Z

Extend generic platform to support Andes QiLai SoC. Signed-off-by: Ben Zong-You Xie Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250814104024.3374698-1-ben717@andestech.com Signed-off-by: Anup Patel

Fix license to compatible BSD-2-Clause

2025-08-28T05:02:46Z

OpenSBI is a BSD project. We need to modify some codes to compatible with BSD-2-Clause license. Signed-off-by: Xiang W Reviewed-by: Ben Zong-You Xie Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250728074334.372355-1-wxjstz@126.com Signed-off-by: Anup Patel

platform: generic: Remove platform override hooks

2025-04-23T07:02:51Z

Now that all of the overrides are modifying generic_platform_ops directly, remove the unused hooks and forwarding functions. The remaining members of struct platform_override match struct fdt_driver, so use that type instead. This allows a future commit to reuse the fdt_driver-based init function. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com Signed-off-by: Anup Patel

platform: generic: Modify platform ops instead of using hooks

2025-04-23T07:02:51Z

Switch all existing platform overrides to use the helper pattern instead of the platform hooks. After this commit, only the .match_table and .init members of struct platform_override are used. There are two minor behavioral differences: - For Allwinner D1, fdt_add_cpu_idle_states() is now called before the body of generic_final_init(). This should have no functional impact. - For StarFive JH7110, if the /chosen/starfive,boot-hart-id property is missing, the code now falls back to using generic_coldboot_harts, instead of accepting any hart. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-7-samuel.holland@sifive.com Signed-off-by: Anup Patel