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<title>opensbi.git/platform/generic/configs/defconfig, branch master</title>
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<updated>2026-08-20T07:32:17Z</updated>
<entry>
<title>lib: utils/reset: Add Metanoia MT2824 system reset driver</title>
<updated>2026-08-20T07:32:17Z</updated>
<author>
<name>Benoît Monin</name>
<email>benoit.monin@bootlin.com</email>
</author>
<published>2026-07-24T15:35:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=f1ab1b45efbdbb8e6ea20557b0e5139d78d15d54'/>
<id>urn:sha1:f1ab1b45efbdbb8e6ea20557b0e5139d78d15d54</id>
<content type='text'>
Add a driver for the system reset function found in Metanoia MT2824 SoC
and enable it in the generic platform configuration.

Originally-by: Jun Chang &lt;jun.chang@metanoia-comm.com&gt;
Signed-off-by: Benoît Monin &lt;benoit.monin@bootlin.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260724-mt5824-v3-2-9a7d17d69974@bootlin.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Add Metanoia MT2824 initial support</title>
<updated>2026-08-20T06:42:38Z</updated>
<author>
<name>Benoît Monin</name>
<email>benoit.monin@bootlin.com</email>
</author>
<published>2026-07-24T15:35:07Z</published>
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<id>urn:sha1:50558221cf0cfc27cfc44fc18e481b61bf45dfde</id>
<content type='text'>
Add the Metanoia MT2824 as a generic platform. This SoC contains two
AX45MP cores from Andes Technology and uses Andes PMU and vendor-specific
extensions.

Originally-by: Jun Chang &lt;jun.chang@metanoia-comm.com&gt;
Signed-off-by: Benoît Monin &lt;benoit.monin@bootlin.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260724-mt5824-v3-1-9a7d17d69974@bootlin.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/mpxy: Add RPMI MPXY driver for logging service group</title>
<updated>2026-07-01T16:00:24Z</updated>
<author>
<name>Subrahmanya Lingappa</name>
<email>subrahmanya.lingappa@oss.qualcomm.com</email>
</author>
<published>2026-06-19T10:34:24Z</published>
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<id>urn:sha1:262571217c75c649115633d8075cb6a40d940733</id>
<content type='text'>
Add RPMI MPXY proxy driver for LOGGING service group so that
S-mode can leverage LOGGING service group implemented by the
platform microcontroller.

Reviewed-by: Rahul Pathak &lt;rahul.pathak@oss.qualcomm.com&gt;
Signed-off-by: Subrahmanya Lingappa &lt;subrahmanya.lingappa@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260619103424.990954-1-subrahmanya.lingappa@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/reset: Add litex SoC reset driver</title>
<updated>2026-06-15T04:40:25Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@gmail.com</email>
</author>
<published>2026-05-29T08:52:32Z</published>
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<id>urn:sha1:dec9141a77058dc941f2d0f07107f7306a995c35</id>
<content type='text'>
Litex SoC controller supports reboot function by toggling the first
bit of the ctrl register. Add a reset driver so other software can
use it.

Signed-off-by: Inochi Amaoto &lt;inochiama@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260529085234.1682842-1-inochiama@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/reset: add SpacemiT P1 PMIC support</title>
<updated>2026-05-11T13:51:31Z</updated>
<author>
<name>Aurelien Jarno</name>
<email>aurelien@aurel32.net</email>
</author>
<published>2026-04-19T14:49:20Z</published>
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<id>urn:sha1:d9637d00bf47a3cc17306fc62e71652c8a83c289</id>
<content type='text'>
The SpacemiT P1 is a PMIC commonly found with SpacemiT CPU like K1. Add
a reset driver for it.

Signed-off-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Tested-by: Anand Moon &lt;linux.amoon@gmail.com&gt;
Link: https://lore.kernel.org/r/20260419150857.2705843-3-aurelien@aurel32.net
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/i2c: add minimal SpacemiT I2C driver</title>
<updated>2026-05-11T13:51:31Z</updated>
<author>
<name>Aurelien Jarno</name>
<email>aurelien@aurel32.net</email>
</author>
<published>2026-04-19T14:49:19Z</published>
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<id>urn:sha1:b10e18ec854a80e938a1fc8cf23beb8f8577cbaf</id>
<content type='text'>
Add a simple SpacemiT I2C driver for basic byte transfers over the I2C
bus, prioritizing simplicity over performance. The driver operates in
PIO mode and does not use interrupts, FIFO, or DMA.

The controller is reset at the start of each transaction to ensure a
known initial state, regardless of prior configuration by the kernel.
This also avoids the need for additional error recovery code.

This will be used for communication with onboard PMIC to reset and
power-off the board.

Signed-off-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Tested-by: Anand Moon &lt;linux.amoon@gmail.com&gt;
Link: https://lore.kernel.org/r/20260419150857.2705843-2-aurelien@aurel32.net
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Tenstorrent Atlantis support</title>
<updated>2026-05-09T15:27:50Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2026-04-24T06:25:19Z</published>
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<id>urn:sha1:6767861c484d07f180f3dd710b5dc59f0c525374</id>
<content type='text'>
Add the Tenstorrent Atlantis as a generic-platform. This initial support
enables the single_fw_region option, and verifies and prints HART PMA
CSR configuration.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add MPXY client driver for RPMI MM service group</title>
<updated>2026-04-06T12:53:25Z</updated>
<author>
<name>Ranbir Singh</name>
<email>ranbir.singh@oss.qualcomm.com</email>
</author>
<published>2026-02-25T06:13:47Z</published>
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<id>urn:sha1:0b041e58c0787f76325da5081e41a13bf304d328</id>
<content type='text'>
Add necessary infra for implementing RPMI Management Mode
service group on platform microcontroller.

Co-authored-by: Sunil V L &lt;sunilvl@oss.qualcomm.com&gt;
Signed-off-by: Ranbir Singh &lt;ranbir.singh@oss.qualcomm.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: sifive: Add initial support for SiFive development platform</title>
<updated>2026-04-06T05:19:21Z</updated>
<author>
<name>Yu-Chien Peter Lin</name>
<email>peter.lin@sifive.com</email>
</author>
<published>2026-02-24T03:17:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=0402b8e3dce9ac71d1c0951cf9716f88ba8dccfc'/>
<id>urn:sha1:0402b8e3dce9ac71d1c0951cf9716f88ba8dccfc</id>
<content type='text'>
Add initial platform support for SiFive development platforms
with the "sifive-dev" compatible string.

Reviewed-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Reviewed-by: Zong Li &lt;zong.li@sifive.com&gt;
Signed-off-by: Yu-Chien Peter Lin &lt;peter.lin@sifive.com&gt;
Link: https://lore.kernel.org/r/20260224031733.3817148-1-peter.lin@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: mips: add P8700 based "eyeq7h" and "boston"</title>
<updated>2026-02-25T13:19:03Z</updated>
<author>
<name>Vladimir Kondratiev</name>
<email>vladimir.kondratiev@mobileye.com</email>
</author>
<published>2026-02-23T14:54:49Z</published>
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<id>urn:sha1:79dfc3a86883e3e1a5ebac96144849ae26adc817</id>
<content type='text'>
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add
2 platforms using this CPU:
- "boston" - FPGA platform developed by MIPS
- "eyeq7h" - automotive platform by Mobileye

Signed-off-by: Vladimir Kondratiev &lt;vladimir.kondratiev@mobileye.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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