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<title>opensbi.git/platform/generic/configs, branch v1.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform/generic/configs?h=v1.3</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/platform/generic/configs?h=v1.3'/>
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<updated>2023-03-09T15:41:20Z</updated>
<entry>
<title>platform: starfive: add PMIC power ops in JH7110 visionfive2 board</title>
<updated>2023-03-09T15:41:20Z</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-03-09T06:19:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=568ea49490d935e01b9a41ef8bb5daf9cb0ef201'/>
<id>urn:sha1:568ea49490d935e01b9a41ef8bb5daf9cb0ef201</id>
<content type='text'>
add reboot and poweroff support. The whole reboot and shutdown
pm op includes shutdown jh7110 pmu device power domain
and access on board pmic register through I2C.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>gpio/starfive: add gpio driver and support gpio reset</title>
<updated>2023-03-01T03:29:33Z</updated>
<author>
<name>minda.chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-02-16T09:21:26Z</published>
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<id>urn:sha1:908be1b85c8ff0695ea226fbbf0ff24a779cdece</id>
<content type='text'>
Add gpio driver and gpio reset function in Starfive
JH7110 SOC platform.

Signed-off-by: minda.chen &lt;minda.chen@starfivetech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>generic/starfive: Add Starfive JH7110 platform implementation</title>
<updated>2023-01-07T10:30:22Z</updated>
<author>
<name>Wei Liang Lim</name>
<email>weiliang.lim@starfivetech.com</email>
</author>
<published>2022-12-29T02:56:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8020df8733b060f01e35b0b2bcb2b41e6b992e9b'/>
<id>urn:sha1:8020df8733b060f01e35b0b2bcb2b41e6b992e9b</id>
<content type='text'>
Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim &lt;weiliang.lim@starfivetech.com&gt;
Reviewed-by: Chee Hong Ang &lt;cheehong.ang@starfivetech.com&gt;
Reviewed-by: Jun Liang Tan &lt;junliang.tan@starfivetech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Add Renesas RZ/Five initial support</title>
<updated>2022-12-12T13:20:56Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:10Z</published>
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<id>urn:sha1:8b1617d13a4200d1ec7d1604e4a4025cc1bcf891</id>
<content type='text'>
This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic/andes: Enable generic platform support for AE350</title>
<updated>2022-12-05T11:54:32Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-12-05T02:03:57Z</published>
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<id>urn:sha1:a36d455182ea0e34d7372110fea215c74f747da2</id>
<content type='text'>
We move andes directory to platform/generic as the necessary fdt
drivers are available, the users can enable the console, timer, ipi,
irqchip and reset devices by adding device tree nodes stated in the
docs/platform/andes-ae350.md.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: add semihosting support</title>
<updated>2022-09-13T12:54:42Z</updated>
<author>
<name>Kautuk Consul</name>
<email>kconsul@ventanamicro.com</email>
</author>
<published>2022-09-12T10:52:53Z</published>
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<id>urn:sha1:7f09fba86e439808e0b40bdf536937c42e1ea2c9</id>
<content type='text'>
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Kautuk Consul &lt;kconsul@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Cadence UART driver</title>
<updated>2022-08-23T03:10:17Z</updated>
<author>
<name>Jun Liang Tan</name>
<email>junliang.tan@linux.starfivetech.com</email>
</author>
<published>2022-08-17T15:40:56Z</published>
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<id>urn:sha1:cbaa9b0333517b3c25bea8d1c71ac8005ff1f727</id>
<content type='text'>
Add Cadence UART driver

Signed-off-by: Jun Liang Tan &lt;junliang.tan@linux.starfivetech.com&gt;
Signed-off-by: Wei Liang Lim &lt;weiliang.lim@linux.starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Use kconfig for enabling/disabling overrides</title>
<updated>2022-08-08T04:04:14Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=d514a8f0dcc3a0a310bbbe33a6ab62d9e10adea8'/>
<id>urn:sha1:d514a8f0dcc3a0a310bbbe33a6ab62d9e10adea8</id>
<content type='text'>
We update generic platform to use kconfig for enabling/disabling
platform overrides. We also enable all platform overrides in generic
platform defconfig.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/gpio: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:04:02Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=5616aa4f4a6d88b1099b90a7e4b1fcf996cf5dab'/>
<id>urn:sha1:5616aa4f4a6d88b1099b90a7e4b1fcf996cf5dab</id>
<content type='text'>
We update gpio drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate gpio
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/i2c: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:57Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=b126ce4a8f5e5f8a45a62ec308e4f74ee590d467'/>
<id>urn:sha1:b126ce4a8f5e5f8a45a62ec308e4f74ee590d467</id>
<content type='text'>
We update i2c drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate i2c
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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