opensbi.git/platform/generic/configs, branch v1.8

platform: generic: eswin: add EIC7700

2025-12-21T15:32:22Z

Initial platform support for ESWIN Computing EIC7700 based on public SoC datasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots fine, and I've tested Geekbench 6.5.0 Preview and got scores on par with the vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and other boards will be implemented in subsequent commits. At this point, only SoC-level warm reset is implemented. The files and functions are intentionally named as eic770x in many places for future enhancements to support the 2 die version of the same SoC, namely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only deals with the single die version, and the assumption is we can be either die with id=0 or id=1, but there's only a single die in the system, or we are only using a single die out of 2. However, the way the SoC handles 2- die greatly affects how we configure it in a 1-die setup. EIC770X address map has die 0/1 memory regions interleaved (see comments in eic770x.c). If only 1 die is connected or active, it creates holes in the address map for those regions corresponding to the remote die. When speculative- execution or HW prefetcher touches data-cacheable regions that happen to fall into those holes, it can trigger bus error. Specifically: - Remote (non-existent) die L3 zero device - Remote (non-existent) die cached memory region - Other holes in Memory Port To make matters worse, EIC770X doesn't have cache coherent DMA, and due to the fact that the P550 core lacks Svpbmt, the SoC maps main memory twice as different regions, so it can bypass cache and fetch the data directly from memory. In address space, we have two memory regions, one as cached, the other as uncached. Thus, we also need an extra PMP entry to protect OpenSBI blob from the uncached window. To do this, platform code requires single_fw_region, otherwise, we'll run out of PMP entries. EIC770X also have several feature disable/enable CSRs accessible in M mode. By default many core features such as speculation and HW prefetch are disabled, and M mode software is responsible of enabling. Hence, introduce 4 new build time tunable parameters to Kconfig, which reflects the values get updated to those CSRs: - ESWIN_EIC770X_FEAT0_CFG - ESWIN_EIC770X_FEAT1_CFG - ESWIN_EIC770X_L1_HWPF_CFG - ESWIN_EIC770X_L2_HWPF_CFG The default values are somewhat optimal for generic workloads. They are dumped when running SiFive's vendor OpenSBI, and in addition, with my own tuning to address the perf regression reported by drmpeg [3] To build the firmware+u-boot blob, Use the following, and docs [4] for testing it with UART boot without flashing: make FW_TEXT_START=0x80000000 \ FW_PAYLOAD_OFFSET=0x200000 \ FW_PAYLOAD_PATH=u-boot-nodtb.bin \ FW_PAYLOAD_FDT_ADDR=0xf8000000 \ FW_FDT_PATH=u-boot.dtb [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual [2] https://github.com/geerlingguy/sbc-reviews/issues/82 [3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15 [4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-6-ganboing@gmail.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive Extensible Cache (EC) driver

2025-12-08T04:31:20Z

Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Co-developed-by: Yong-Xuan Wang Signed-off-by: Yong-Xuan Wang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive PL2 controller

2025-12-08T04:31:05Z

SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin Signed-off-by: Eric Lin Co-developed-by: Zong Li Signed-off-by: Zong Li Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel

platform: ariane: Move ariane platform from fpga to generic

2025-11-05T15:52:41Z

The Ariane framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the Ariane platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for performance

2025-11-04T05:05:59Z

Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for device power

2025-11-04T05:04:01Z

Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for voltage

2025-11-04T05:02:57Z

Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel

lib: utils/suspend: Add SiFive SMC0 driver

2025-10-28T05:58:10Z

The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/hsm: Add SiFive TMC0 driver

2025-10-28T05:58:03Z

The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Reviewed-by: Cyan Yang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel

utils: cache: Add SiFive ccache controller

2025-10-28T05:57:51Z

SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Vincent Chen Co-developed-by: Nick Hu Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel