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<title>opensbi.git/platform/generic/include/thead, branch master</title>
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<updated>2025-01-30T05:00:45Z</updated>
<entry>
<title>lib: sbi: pmu: fix usage of sbi_pmu_irq_bit()</title>
<updated>2025-01-30T05:00:45Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2025-01-10T13:15:50Z</published>
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<id>urn:sha1:3943ddbaab00247b391128ae0a1f9258d4007f4f</id>
<content type='text'>
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage
was still hardcoded in various places. This led to change the returned
value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask
since it returns an 'int' and we need to obtain the bit number itself to
handle it in the IRQs handlers. Add a similar function to return the
irq mask which can also be used where the mask is required rather than
the bit itself.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: separate T-Head PMU Errata</title>
<updated>2024-05-09T12:39:05Z</updated>
<author>
<name>Yangyu Chen</name>
<email>cyy@cyyself.name</email>
</author>
<published>2024-04-21T15:52:08Z</published>
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<id>urn:sha1:33e21c9476e225064464ad045ce11cf58c2c3204</id>
<content type='text'>
As Guo Ren said from the kernel mailing list [1], future T-Head CPUs,
including the newer versions of T-Head C908, will feature standard
Sscofpmf extension. For these CPUs, T-Head's implementation of PMU
Overflow Interrupts may not needed anymore. In this case, we shouldn't
apply T-Head PMU for all T-Head CPUs. Thus, this patch separated T-Head PMU
errata.

[1] https://lore.kernel.org/linux-riscv/Zh9sUUUT09LZb0MO@gmail.com/

Signed-off-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Reviewed-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: separate implement of T-HEAD c9xx errata</title>
<updated>2023-11-14T16:23:50Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-07T03:06:30Z</published>
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<id>urn:sha1:492d9b153d00ec2fc2fec89ded42e71df52e27aa</id>
<content type='text'>
Separate the implement of T-HEAD c9xx errata to allow any platform
with bug related to c9xx cores can use it.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: separate implement of T-HEAD c9xx pmu</title>
<updated>2023-11-14T16:23:45Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-07T03:06:29Z</published>
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<id>urn:sha1:8e941e7fe3b8244107832b931980006bf9b0dc55</id>
<content type='text'>
Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: move to thead c9xx header to vendor specific postion</title>
<updated>2023-11-14T16:23:42Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-07T03:06:28Z</published>
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<id>urn:sha1:c1a69874476810aa47bb1ca8bbe7697f855dba5f</id>
<content type='text'>
The CSR encoding for t-head c9xx cores is shared across all the
platforms with these cores. So move header thead_c9xx.h to the
thead subdir.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Acked-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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