opensbi.git/platform/generic/include, branch master

platform: generic: spacemit: k1: fix wrong address definitions

2026-06-28T05:46:36Z

PMU_AP_CORE2_IDLE_CFG and PMU_AP_CORE3_IDLE_CFG are not continuous with PMU_AP_CORE0_IDLE_CFG and PMU_AP_CORE1_IDLE_CFG. They are at PMU AP base + 0x160 and + 0x164, matching the vendor OpenSBI definitions. After fixing these addresses, the intermediate cluster offset macros are redundant now, so define the wakeup and idle registers directly as PMU_AP_BASE offsets. This makes the actual register addresses easier to inspect and compare against the vendor code. C1_RVBADDR_HI_ADDR is also corrected according to the vendor OpenSBI definition. This was tested by writing an invalid value to the corrected address, which prevents cluster1 CPUs from coming online, while doing the same with the old address does not affect SMP boot. Fixes: 1f84ec2a ("platform: generic: spacemit: add K1") Signed-off-by: Junhui Liu Link: https://lore.kernel.org/r/20260623-k1-fix-addr-v1-1-3dbde8c03bd6@pigmoral.tech Signed-off-by: Anup Patel

platform: generic: eswin: Add eic770x_hsm and fix warm reset issues

2026-06-15T05:08:09Z

During warm reset, my EIC770X/Hifive Premier P550 can sometimes encounter memory corruption issue crashing Linux boot. Currently the issue is mitigated by having a sbi_printf before writing to the reset register. I analyzed the issue further since then. From the SoC datasheet[1], it's recommended to implement power-down flow as: a. Designate a primary core, and let it broadcast requests to other cores to execute a CEASE insn. Primary core also notifies an "Externel Agent" to start monitoring. b. Primary core waits for other cores to CEASE before it CEASEs. c. "External Agent" waits for primary core to CEASE before resets the Core Complex. It's possible that EIC770X can trigger undefined behavior if the core complex is reset while the harts are actively running. The sbi_printf in the reset handler effectively hides the problem by delaying the reset -- by the time sbi_printf finishes, all other harts will have already landed in the loop in sbi_hsm_hart_wait(), which parks the hart. Without the sbi_printf, I confirmed that other harts haven't reached sbi_hsm_hart_wait yet before current hart resets the SoC. (by debugging) To safely reset, and inspired by the datasheet, the warm reset logic in eic770x.c now use the current hart as both primary core and the "External Agent", and other harts as secondary cores. It leverages the HSM framework and a new eic770x_hsm device to CEASE other harts, and wait for them to CEASE before resets the SoC. with the sbi_printf before reset removed, and this logic in place, stress test shows that the memory corruption issue no longer occurs. The new eic770x_hsm device is only used for the reset-CEASE logic at the moment, and may be extended to a fully functional HSM device in the future. [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual Fixes: e5797e0688c1 ("platform: generic: eswin: add EIC7700") Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260605075708.96-3-ganboing@gmail.com Signed-off-by: Anup Patel

platform: generic: Optimize extensions_init() to parse ISA extensions once

2026-06-12T10:38:29Z

Instead of parsing ISA extensions separately for each hart in the generic_extensions_init() function, it is better to parse ISA extensions for all available harts in the cold boot path. Also, this allows us to remove fdt_isa_bitmap from scratch space and directly initialize "extensions" in struct sbi_hart_features for each hart. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

platform: generic: Tenstorrent Atlantis support

2026-05-09T15:27:50Z

Add the Tenstorrent Atlantis as a generic-platform. This initial support enables the single_fw_region option, and verifies and prints HART PMA CSR configuration. Signed-off-by: Nicholas Piggin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com Signed-off-by: Anup Patel

platform: generic: p8700: fix MIPS specific CSRs

2026-02-25T13:19:03Z

P8700 has MIPS specific CSRs. Fix the list, adding few missing ones and remove few non-existing Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-22-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

platform: generic: mips p8700: dump MMIO regions

2026-02-25T13:19:03Z

Debug print MMIO regions Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-20-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2

2026-02-25T13:19:03Z

CPU clusters 1 and 2 cannot access NCORE registers through AUX ports. AUX ports of clusters 1 and 2 are connected to NCORE through east port. East port has no access to NCORE registers address space. Re-route NCORE registers range to MEM port by re-configuring MMIO regions in the GCR. REsulting map is as below. Mind a gap between regions [1] and [2]; this gap covering NCORE registers now routed to the default MEM port Cluster 0: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 1: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Cluster 2: 4 MMIO regions [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA [3] : --disabled-- Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

platform: generic: mips eyeq7h: synchronize timers across clusters

2026-02-25T13:19:03Z

Use eyeq7 specific method to synchronously restart architectural mtimer and eyeq7h specific high-resolution timer with common hardware trigger. This ensures all timers are precisely in sync Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

platform: generic: mips p8700: synchronize hi-res timers

2026-02-25T13:19:03Z

There's high-resolution (1GHz) timer found in the p8700 cluster. This timer used for precise time measurement by platform specific software. Synchronize this proprietary timers to reference in cluster 0. Procedure borrowed from the aclint mtimer. Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com Signed-off-by: Anup Patel

platform: generic: mips p8700: use SBI bitfield manipulator macros

2026-02-25T13:19:03Z

Switch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com Signed-off-by: Anup Patel