opensbi.git/platform/generic/include, branch v1.3

platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

2023-04-14T12:05:04Z

platform: generic: renesas: rzfive: Add support to configure the PMA

2023-02-27T06:05:01Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

include: sbi: Remove extid parameter from vendor_ext_provider() callback

2023-02-27T05:56:37Z

The extid parameter of vendor_ext_provider() is redundant so let us remove it. Signed-off-by: Anup Patel

lib: sbi: Align SBI vendor extension id with mvendorid CSR

2023-02-27T05:56:35Z

As-per the SBI specification, the lower 24bits of the SBI vendor extension id is same as lower 24bits of the mvendorid CSR. We update the SBI vendor extension id checking based on above. Signed-off-by: Anup Patel

platform: andes/ae350: Implement hart hotplug using HSM extension

2023-01-22T12:03:03Z

Add hart_start() and hart_stop() callbacks for the multi-core ae350 platform, it utilizes the ATCSMU to put the harts into power-gated deep sleep mode. The programming sequence is stated as below: 1. Set the wakeup events to PCSm_WE 2. Set the sleep command to PCSm_CTL 3. Set the reset vector to HARTm_RESET_VECTOR_{LO|HI} 4. Write back and invalidate D-cache by executing the CCTL command L1D_WBINVAL_ALL 5. Disable I/D-cache by clearing mcache_ctl.{I|D}C_EN 6. Disable D-cache coherency by clearing mcache_ctl_.DC_COHEN 7. Wait for mcache_ctl.DC_COHSTA to be cleared to ensure the previous step is completed 8. Execute WFI Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: generic: Allow platform_override to perform firmware init

2023-01-07T10:28:54Z

We add a generic platform override callback to allow platform specific firmware init. Signed-off-by: Wei Liang Lim Reviewed-by: Chee Hong Ang Reviewed-by: Jun Liang Tan Reviewed-by: Anup Patel

platform: generic: Allow platform_override to select cold boot HART

2023-01-07T10:28:52Z

We add a generic platform override callback to allow platform specific selection of cold boot HART. Signed-off-by: Anup Patel

platform: generic: allwinner: add support for c9xx pmu

2022-10-13T04:22:09Z

With the T-HEAD C9XX cores being designed before or during ratification of the SSCOFPMF extension, they implement a PMU extension that behaves very similar but not equal to it by providing overflow interrupts though in a slightly different registers format. The sun20i-d1 is using this core. So implement the necessary overrides to allow its pmu to be used via the standard sbi-pmu extension. For now it's also the only soc using this core, so keep the additional code in the d1-space for now. Reviewed-by: Andrew Jones Reviewed-by: Guo Ren Reviewed-by: Anup Patel Signed-off-by: Heiko Stuebner

platform: generic: add extensions_init handler and platform-override

2022-10-13T04:22:06Z

Init of non-standard extensions is a platform-specific thing, so allow generic platforms to do this via a platform-override. Reviewed-by: Andrew Jones Reviewed-by: Guo Ren Reviewed-by: Anup Patel Signed-off-by: Heiko Stuebner

platform: generic: add overrides for vendor extensions

2022-06-13T05:47:38Z

Allow the vendor_ext_check and vendor_ext_provider APIs of the generic platform to be overridden by other platforms Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel