opensbi.git/platform/generic/include, branch v1.4

lib: sbi: Allow ecall handlers to directly update register state

2023-12-19T10:26:37Z

Some of the upcoming SBI extensions (such as SSE) will directly update register state so improve the prototype of ecall handler to accommodate this. Further, this flexibility allows us to push the trap redirection from sbi_ecall_handler() to the sbi_ecall_legacy_handler(). Signed-off-by: Anup Patel

platform: andes: Factor out is_andes() helper

2023-12-06T12:33:12Z

We will need is_andes(45) in the following patch, so factor out the code that parses marchid to make it reusable for checking any Andes CPU variants. Also improves the comment in ae350_hart_start(). Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: andes: Add Andes custom PMU support

2023-12-06T12:23:45Z

Before the ratification of Sscofpmf, the Andes PMU extension was designed to support the sampling and filtering with hardware performance counters (zihpm), it works with the current SBI PMU extension and Linux SBI PMU driver. We implement 1) the PMU device callbacks that update the corresponding bits on custom CSRs, 2) extentions_init() to detect the hardware support of Andes PMU and initialize the per-hart PMU related CSR, and 3) pmu_init() to register PMU device and populate event mappings. Also define a andes_pmu_setup() function which is in preparation for adding default PMU mappings in andes_hpm.h Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel

platform: generic: Introduce pmu_init() platform override

2023-12-06T12:19:59Z

Add pmu_init() platform override, which will be used to register PMU device and populate event mappings. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: include: andes45: Add PMU related CSR defines

2023-12-06T12:01:36Z

Add CSR definitions for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar

platform: generic: thead: separate implement of T-HEAD c9xx errata

2023-11-14T16:23:50Z

Separate the implement of T-HEAD c9xx errata to allow any platform with bug related to c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx pmu

2023-11-14T16:23:45Z

Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: move to thead c9xx header to vendor specific postion

2023-11-14T16:23:42Z

The CSR encoding for t-head c9xx cores is shared across all the platforms with these cores. So move header thead_c9xx.h to the thead subdir. Signed-off-by: Inochi Amaoto Acked-by: Guo Ren Reviewed-by: Anup Patel

platform: Allow platforms to specify the size of tlb fifo

2023-09-10T05:51:05Z

For some platforms with a particularly high number of harts, if the tlb fifo is too small, it case harts to wait. Platforms should be allowed to specify the size of the tlb fifo. Signed-off-by: Xiang W Signed-off-by: Xing Xiaoguang Reviewed-by: Anup Patel

platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

2023-04-14T12:05:04Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Yu Chien Peter Lin