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<title>opensbi.git/platform/generic/platform.c, branch v1.4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform/generic/platform.c?h=v1.4</id>
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<updated>2023-12-19T10:26:37Z</updated>
<entry>
<title>lib: sbi: Allow ecall handlers to directly update register state</title>
<updated>2023-12-19T10:26:37Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-12-11T15:29:14Z</published>
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<id>urn:sha1:3284bea83368de2ced244d5b2b0eaeaae812a08d</id>
<content type='text'>
Some of the upcoming SBI extensions (such as SSE) will directly
update register state so improve the prototype of ecall handler
to accommodate this. Further, this flexibility allows us to
push the trap redirection from sbi_ecall_handler() to the
sbi_ecall_legacy_handler().

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>platform: generic: Fine tune fw_platform_calculate_heap_size()</title>
<updated>2023-12-19T10:26:37Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-12-11T08:03:58Z</published>
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<id>urn:sha1:80169b25f8a9a7cb8becceff9a414900919527c6</id>
<content type='text'>
Let's use SBI_TLB_INFO_SIZE instead of hard-coded 0x40 in
fw_platform_calculate_heap_size() to fine tune the heap size
required for per-hart TLB fifos.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>platform: recalculate heap size to support new tlb entry number</title>
<updated>2023-12-11T03:53:24Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-12-10T09:44:54Z</published>
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<id>urn:sha1:87aa3069d14b52bf87cb14d8f6b3ed51b45465ea</id>
<content type='text'>
Previous patch introduced a change that using hart count as the default
number of tlb entries in the fifo. This makes the default tlb fifo size
grow in square with the number of harts. So the default heap size is
not enough to allocate tlb fifo when the hart count is big.

Fixes: 52fd64b ("platform: Uses hart count as the default size of tlb info")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Introduce pmu_init() platform override</title>
<updated>2023-12-06T12:19:59Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-11-30T12:42:04Z</published>
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<id>urn:sha1:effd89aa055c7cc6a167f55d333c2b7ba035614b</id>
<content type='text'>
Add pmu_init() platform override, which will be used to register
PMU device and populate event mappings.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>sbi: sbi_pmu: Improve sbi_pmu_init() error handling</title>
<updated>2023-12-06T11:54:38Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-11-30T12:42:00Z</published>
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<id>urn:sha1:291403f6f29dd119d94ac99303c94dadcb5496c3</id>
<content type='text'>
This patch makes the following changes:

- As sbi_platform_pmu_init() returns a negative error code on
  failure, let sbi_pmu_init() print out the error code with
  sbi_dprintf().

- In order to distinguish the SBI_EFAIL error returned by
  sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
  that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
  generic_pmu_init() ignores such case.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: change sbi_hart_features.extensions as an array</title>
<updated>2023-11-17T07:53:49Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-10-30T16:39:40Z</published>
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<id>urn:sha1:6602e11de375b761d778808cc38645fce314c4fa</id>
<content type='text'>
In the future there may be a lot of ISA extensions, a 'long' may not
be able to accommodate, changed to an array for the future.

Addresses-Coverity-ID: 1568357 Out-of-bounds access
Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions()
implementation")
Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Uses hart count as the default size of tlb info</title>
<updated>2023-11-16T04:23:45Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-10-12T08:33:28Z</published>
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<id>urn:sha1:52fd64b82c0de0fdf386c96f2b9e1c4c3e56d80d</id>
<content type='text'>
For platform with high number of harts, it is better to auto detect a
suitable number of entries in tlb fifo. Since allocating tlb entry for
all online harts can reduce the wait time significantly, using the
number of the online harts can make most platforms happy. This auto
detection can avoid most duplicate code for setting tlb fifo size.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Acked-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Allow platforms to specify the size of tlb fifo</title>
<updated>2023-09-10T05:51:05Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-09-06T13:10:03Z</published>
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<id>urn:sha1:cacfba32cc9541b7b9f838df43c1f2bd43222d3a</id>
<content type='text'>
For some platforms with a particularly high number of harts, if the
tlb fifo is too small, it case harts to wait. Platforms should be
allowed to specify the size of the tlb fifo.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Signed-off-by: Xing Xiaoguang &lt;xiaoguang.xing@sophgo.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add detection of Smepmp from ISA string in FDT</title>
<updated>2023-07-13T06:42:58Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-07-12T04:34:31Z</published>
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<id>urn:sha1:d72f5f17478dfef3df817339a0f02cfdb77a1dc1</id>
<content type='text'>
- Add function to parse ISA string in FDT.
- Set Smepmp feature bit in extensions if "smepmp" string is found in ISA string.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: reset: Move fdt_reset_init into generic_early_init</title>
<updated>2023-06-21T05:42:42Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2023-06-18T15:07:16Z</published>
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<id>urn:sha1:27c957a43b030523baf931a3b8ef002418fb27ad</id>
<content type='text'>
The fdt_reset_thead driver needs to modify the __reset_thead_csr_stub
text region for the secondary harts booting. After that, the
sbi_hart_pmp_configure may lock down the text region with M_READABLE &amp;
M_EXECUTABLE attributes in the future. Currently, the M_READABLE &amp;
M_EXECUtABLE have no effect on m-mode, the L-bit in pmpcfg csr is
useless for the current opensbi scenario. See:

Priv-isa-spec 3.7.1.2. Locking and Privilege Mode
When the L bit is clear, any M-mode access matching the PMP entry will
succeed; the R/W/X permissions apply only to S and U modes.

That's why current fdt_reset_thead could still work well after commit:
230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW
regions"). So this patch fixes up a fake bug for the M-mode permission
setting of the future.

Fixes: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions")
Link: http://lists.infradead.org/pipermail/opensbi/2023-June/005176.html
Reported-by: Jessica Clarke &lt;jrtc27@jrtc27.com&gt;
Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Signed-off-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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