opensbi.git/platform/generic/renesas, branch master

Fix license to compatible BSD-2-Clause

2025-08-28T05:02:46Z

OpenSBI is a BSD project. We need to modify some codes to compatible with BSD-2-Clause license. Signed-off-by: Xiang W Reviewed-by: Ben Zong-You Xie Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250728074334.372355-1-wxjstz@126.com Signed-off-by: Anup Patel

platform: generic: Remove platform override hooks

2025-04-23T07:02:51Z

Now that all of the overrides are modifying generic_platform_ops directly, remove the unused hooks and forwarding functions. The remaining members of struct platform_override match struct fdt_driver, so use that type instead. This allows a future commit to reuse the fdt_driver-based init function. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com Signed-off-by: Anup Patel

platform: generic: Modify platform ops instead of using hooks

2025-04-23T07:02:51Z

Switch all existing platform overrides to use the helper pattern instead of the platform hooks. After this commit, only the .match_table and .init members of struct platform_override are used. There are two minor behavioral differences: - For Allwinner D1, fdt_add_cpu_idle_states() is now called before the body of generic_final_init(). This should have no functional impact. - For StarFive JH7110, if the /chosen/starfive,boot-hart-id property is missing, the code now falls back to using generic_coldboot_harts, instead of accepting any hart. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-7-samuel.holland@sifive.com Signed-off-by: Anup Patel

platform: rzfive: Call andes_pma_setup_regions() only during cold boot

2025-04-23T07:02:50Z

This function accesses the FDT blob, which means it is only valid to call during cold boot, before a lower privilege level has an opportunity to clobber that memory. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250325234342.711447-3-samuel.holland@sifive.com Signed-off-by: Anup Patel

platform: generic: Pass FDT to early/final_init overrides

2024-08-24T07:32:54Z

Several of these override functions access the FDT blob. Explicitly indicate which callbacks are allowed to modify the FDT blob by passing the parameter as a possibly-const pointer. This also reduces code size by deduplicating the call to fdt_get_address(). Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

platform: andes: Change all occurrences of andes45 to andes

2024-05-09T12:27:51Z

To make the framework suit all Andes CPUs, change all occurrences of andes45 to andes. In addition, we fix some coding style problems and remove an unused macro in andes.h. Signed-off-by: Ben Zong-You Xie Reviewed-by: Anup Patel

platform: rzfive: Enable Andes PMU for RZ/Five

2023-12-06T12:27:28Z

Enable Andes PMU extension support for RZ/Five. We also staticize renesas_rzfive_early_init() as it is not used outside of this unit. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

2023-04-14T12:05:04Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Yu Chien Peter Lin

platform: generic: renesas: rzfive: Configure the PMA region

2023-02-27T06:06:06Z

On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA and populate this region as PMA reserve DT node with shared DMA pool and no-map flags set so that Linux drivers requesting any DMA'able memory go through this region. PMA node passed to the above stack: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: renesas/rzfive: Configure Local memory regions as part of root domain

2023-01-23T05:59:03Z

Renesas RZ/Five RISC-V SoC has Instruction local memory and Data local memory (ILM & DLM) mapped between region 0x30000 - 0x4FFFF. When a virtual address falls within this range, the MMU doesn't trigger a page fault; it assumes the virtual address is a physical address which can cause undesired behaviours for statically linked applications/libraries. To avoid this, add the ILM/DLM memory regions to the root domain region of the PMPU with permissions set to 0x0 for S/U modes so that any access to these regions gets blocked and for M-mode we grant full access (R/W/X). Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel