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<title>opensbi.git/platform/generic, branch release-1.5.x</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform/generic?h=release-1.5.x</id>
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<updated>2024-06-18T10:49:47Z</updated>
<entry>
<title>platform: generic: andes: Add support for RV32 to set up PMA</title>
<updated>2024-06-18T10:49:47Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-05-31T05:21:08Z</published>
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<id>urn:sha1:52dcf351cddf12081acc921c135df265f9d2f243</id>
<content type='text'>
Like PMP, the behaviors to configure PMA will be different from
RV64 and RV32. RV64 uses two Andes custom CSRs, pmacfg0 and pmacfg2,
but RV32 uses four Andes custom CSRs, pmacfg0 ~ pmacfg3. This patch
adds support to PMA for RV32.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: andes: Refine Andes PMA related code</title>
<updated>2024-06-18T10:45:22Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-05-31T05:19:04Z</published>
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<id>urn:sha1:f09f16430ae7b3543616a38df4411fea8f026759</id>
<content type='text'>
This patch refines the Andes PMA related code. The main change is
refactor andes_pma_[read|write]_cfg() and andes_pma_[read|write]_addr()
into new functions andes_pma_[read|write]_num().

Also, fix some coding style problems.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: add Sophgo CV18XX/SG200X series</title>
<updated>2024-05-16T04:48:44Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2024-05-14T04:53:40Z</published>
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<id>urn:sha1:2bed4c1c57a7775bcef534934cab5c83b45b954f</id>
<content type='text'>
The Sophgo CV18XX/SG200X series SoCs have a standard C906
core. Add support for it.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>utils/reset: Add SG2042 hwmon MCU support.</title>
<updated>2024-05-15T06:17:15Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2024-04-28T01:24:10Z</published>
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<id>urn:sha1:ea9cf6aa28ca308f6a2561da5b570ed9f6148978</id>
<content type='text'>
SG2042 uses an onboard MCU to provide reset function.
Add reset driver to support this onboard MCU.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: add Canaan Kendryte K230</title>
<updated>2024-05-09T12:40:25Z</updated>
<author>
<name>Yangyu Chen</name>
<email>cyy@cyyself.name</email>
</author>
<published>2024-04-21T15:52:09Z</published>
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<id>urn:sha1:019a8e69a1dc0c0f011fabd0372e1ba80e40dd7c</id>
<content type='text'>
Canaan Kendryte K230 SoC has T-Head C908 cores inside. The dt-binding has
been merged into the linux kernel [1]. However, it has early version of
C908 core which does not have Sscofpmf and need to use T-Head PMU
extension. Thus, we add a K230 compatible string to thead_generic_match
and set quirk for T-Head PMU.

[1] https://lore.kernel.org/linux-riscv/tencent_4D85743622F39109466913393EE2F6C5980A@qq.com/

Signed-off-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Reviewed-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: thead: separate T-Head PMU Errata</title>
<updated>2024-05-09T12:39:05Z</updated>
<author>
<name>Yangyu Chen</name>
<email>cyy@cyyself.name</email>
</author>
<published>2024-04-21T15:52:08Z</published>
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<id>urn:sha1:33e21c9476e225064464ad045ce11cf58c2c3204</id>
<content type='text'>
As Guo Ren said from the kernel mailing list [1], future T-Head CPUs,
including the newer versions of T-Head C908, will feature standard
Sscofpmf extension. For these CPUs, T-Head's implementation of PMU
Overflow Interrupts may not needed anymore. In this case, we shouldn't
apply T-Head PMU for all T-Head CPUs. Thus, this patch separated T-Head PMU
errata.

[1] https://lore.kernel.org/linux-riscv/Zh9sUUUT09LZb0MO@gmail.com/

Signed-off-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Reviewed-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: andes: Change all occurrences of andes45 to andes</title>
<updated>2024-05-09T12:27:51Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-04-19T03:58:24Z</published>
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<id>urn:sha1:2b93ce0954d594a1c4919f02187bbf7177ed412d</id>
<content type='text'>
To make the framework suit all Andes CPUs, change all occurrences of
andes45 to andes.

In addition, we fix some coding style problems and remove an unused
macro in andes.h.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: andes: Rename files with the prefix andes45</title>
<updated>2024-05-09T12:26:50Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2024-04-19T03:58:23Z</published>
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<id>urn:sha1:f68b3aed9d7bc74f61deb817feeb982809655c51</id>
<content type='text'>
Rename files with the prefix andes45 to andes.

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: remove FW_TEXT_START</title>
<updated>2024-04-10T04:20:24Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2024-04-08T15:27:42Z</published>
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<id>urn:sha1:d4d2582eef7aac442076f955e4024403f8ff3d96</id>
<content type='text'>
Now opensbi can run at any address via dynamic relocation. We can
remove FW_TEXT_START.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: allwinner: Optimize current hart scratch access</title>
<updated>2024-04-05T12:04:25Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-03-18T14:49:29Z</published>
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<id>urn:sha1:f5375bc15e9f3e577dfc24f9095a3e37246a3fa3</id>
<content type='text'>
The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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