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<title>opensbi.git/platform/nuclei, branch v0.9</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform/nuclei?h=v0.9</id>
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<updated>2020-12-01T11:40:31Z</updated>
<entry>
<title>lib: sbi: Improve system reset platform operations</title>
<updated>2020-12-01T11:40:31Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-11-24T06:29:05Z</published>
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<id>urn:sha1:5c429ae2133e1a82b81403146a3e38e2b4b8350e</id>
<content type='text'>
To implement the SBI SRST extension, we need two platform operations
for system reset:
1) system_reset_check() - This operation will check whether given
   reset type and reason are supported by the platform
2) system_reset() - This operation will do the actual platform
   system reset and it will not return if reset type and reason
   are supported by the platform

This patch updates system reset related code everywhere as-per above.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Update Nuclei ux600 platform support</title>
<updated>2020-06-17T15:36:40Z</updated>
<author>
<name>Huaqi Fang</name>
<email>578567190@qq.com</email>
</author>
<published>2020-06-12T09:01:49Z</published>
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<id>urn:sha1:518e85cccb18a6dfe71fc8d1227c8f8d74527dc9</id>
<content type='text'>
Changes are made to support our FPGA evaluation board,
it has DDR memory(0xA0000000-0xB0000000).

* Adapt the config.mk to match FPGA evaluation board DDR memory address
* Since the RISC-V CPU core frequency of FPGA might change, so we use the
  fixed TIMER frequency to measure the real CPU core frequency.
* And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation
  board when CPU core frequency is about 8MHz, otherwise the UART input
  will not work correctly.

Signed-off-by: Huaqi Fang &lt;578567190@qq.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Allow CLINT functions to be used for multiple CLINTs</title>
<updated>2020-05-23T05:06:43Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-12T13:08:31Z</published>
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<id>urn:sha1:a9a97511851198559e75640a9e5e67f65695dc2e</id>
<content type='text'>
We extend CLINT cold init function to have a "struct clint_data *"
parameter pointing to CLINT details. This allows platforms to use
CLINT functions for multiple CLINT instances.

When multiple CLINTs are present, the platform can also provide
one of the CLINT as reference CLINT for other CLINTs. This will
help CLINTs to sync their time value with reference CLINT using
a time_delta computed in warm init function.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Allow PLIC functions to be used for multiple PLICs</title>
<updated>2020-05-23T05:06:29Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-12T07:27:52Z</published>
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<id>urn:sha1:446a9c6d1eb97fcedd6a94ac76d15e941a6087a8</id>
<content type='text'>
We extend all PLIC functions to have a "struct plic_data *"
parameter pointing to PLIC details. This allows platforms to
use these functions for multiple PLIC instances.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Remove redundant parameters from PLIC init functions</title>
<updated>2020-05-23T05:06:26Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-12T04:44:43Z</published>
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<id>urn:sha1:73d6ef3b2933ccf0b3a8a0ba110bf53ad9720b51</id>
<content type='text'>
The "target_hart" and "hart_count" parameters of PLIC cold and
warm init functions are only used for sanity checks and not
required in PLIC initialization.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Add Nuclei UX600 platform</title>
<updated>2020-04-29T09:36:36Z</updated>
<author>
<name>Huaqi Fang</name>
<email>578567190@qq.com</email>
</author>
<published>2020-04-28T14:43:40Z</published>
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<id>urn:sha1:4781545512537effc97ffb07079076cf0819842c</id>
<content type='text'>
* Nuclei UX600 is a 64-bit RISC-V core developed
  by Nuclei System Technology, see https://nucleisys.com/product.php

* The ISA is configurable in hardware on your demand

Signed-off-by: Huaqi Fang &lt;578567190@qq.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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