opensbi.git/platform, branch release-1.3.x

gpio/desginware: add Synopsys DesignWare APB GPIO support

2023-07-07T04:34:59Z

Add a driver for the Synopsys DesignWare APB GPIO IP block found in many SoCs. Signed-off-by: Ben Dooks Reviewed-by: Anup Patel

lib: reset: Move fdt_reset_init into generic_early_init

2023-06-21T05:42:42Z

The fdt_reset_thead driver needs to modify the __reset_thead_csr_stub text region for the secondary harts booting. After that, the sbi_hart_pmp_configure may lock down the text region with M_READABLE & M_EXECUTABLE attributes in the future. Currently, the M_READABLE & M_EXECUtABLE have no effect on m-mode, the L-bit in pmpcfg csr is useless for the current opensbi scenario. See: Priv-isa-spec 3.7.1.2. Locking and Privilege Mode When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes. That's why current fdt_reset_thead could still work well after commit: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions"). So this patch fixes up a fake bug for the M-mode permission setting of the future. Fixes: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions") Link: http://lists.infradead.org/pipermail/opensbi/2023-June/005176.html Reported-by: Jessica Clarke Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Anup Patel

platform/lib: Set no-map attribute on all PMP regions

2023-06-15T12:57:17Z

This reverts commit 6966ad0abe70 ("platform/lib: Allow the OS to map the regions that are protected by PMP"). It was thought at the time of this commit that allowing the kernel to map PMP protected regions was safe but it is actually not: for example, the hibernation process will try to access any linear mapping page and then will fault on such mapped PMP regions [1]. Another issue is that the device tree specification [2] states that a !no-map region must be declared as EfiBootServicesData/Code in the EFI memory map which would make the PMP protected regions reclaimable by the kernel. And to circumvent this, RISC-V edk2 diverges from the DT specification to declare those regions as EfiReserved. The no-map attribute was removed to allow the kernel to use hugepages larger than 2MB to map the linear mapping to improve the performance but actually a recent talk from Mike Rapoport [3] stated that the performance benefit was marginal. For all those reasons, let's mark all the PMP protected regions as "no-map". [1] https://lore.kernel.org/linux-riscv/CAAYs2=gQvkhTeioMmqRDVGjdtNF_vhB+vm_1dHJxPNi75YDQ_Q@mail.gmail.com/ [2] "3.5.4 /reserved-memory and UEFI" https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4-rc1/devicetree-specification-v0.4-rc1.pdf [3] https://lwn.net/Articles/931406/ Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Xiang W

platform: Allow platforms to specify heap size

2023-06-05T10:15:33Z

We extend struct sbi_platform and struct sbi_scratch to allow platforms specify the heap size to the OpenSBI firmwares. The OpenSBI firmwares will use this information to determine the location of heap and provide heap base address in per-HART scratch space. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones

platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

2023-04-14T12:05:04Z

platform: starfive: add PMIC power ops in JH7110 visionfive2 board

2023-03-09T15:41:20Z

add reboot and poweroff support. The whole reboot and shutdown pm op includes shutdown jh7110 pmu device power domain and access on board pmic register through I2C. Signed-off-by: Minda Chen Reviewed-by: Anup Patel

gpio/starfive: add gpio driver and support gpio reset

2023-03-01T03:29:33Z

Add gpio driver and gpio reset function in Starfive JH7110 SOC platform. Signed-off-by: minda.chen Reviewed-by: Anup Patel

platform: generic: Add system suspend test

2023-02-27T14:20:51Z

When the system-suspend-test property is present in the domain config node as shown below, implement system suspend with a simple 5 second delay followed by a WFI. This allows testing system suspend when the low-level firmware doesn't support it. / { chosen { opensbi-domains { compatible = "opensbi,domain,config"; system-suspend-test; }; Signed-off-by: Andrew Jones Reviewed-by: Anup Patel

platform: generic: renesas: rzfive: Configure the PMA region

2023-02-27T06:06:06Z

On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA and populate this region as PMA reserve DT node with shared DMA pool and no-map flags set so that Linux drivers requesting any DMA'able memory go through this region. PMA node passed to the above stack: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: generic: renesas: rzfive: Add support to configure the PMA

2023-02-27T06:05:01Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel