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<title>opensbi.git/platform, branch v0.7</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform?h=v0.7</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/platform?h=v0.7'/>
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<updated>2020-03-28T08:11:03Z</updated>
<entry>
<title>platform: thead/c910: Use HSM extension to boot secondary cores</title>
<updated>2020-03-28T08:11:03Z</updated>
<author>
<name>Liu Yibin</name>
<email>yibin_liu@c-sky.com</email>
</author>
<published>2020-03-27T03:31:48Z</published>
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<id>urn:sha1:e5a7f556ce22984128bed0a336551a968c818450</id>
<content type='text'>
Remove custom vendor extension and use HSM extension
to boot secondary cores

Signed-off-by: Liu Yibin &lt;yibin_liu@c-sky.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>platform: openpiton: Read the device configurations from device tree</title>
<updated>2020-03-24T08:03:39Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-03-23T19:48:59Z</published>
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<id>urn:sha1:4c374511fd893ee4a7c7f1b225307f7d257e6bf1</id>
<content type='text'>
OpenPiton is designed to run on different FPGAs with different
configurations. Use the fdt parser to retrieve the required values
from device tree instead of using fixed values.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Tested-by: Jonathan Balkind &lt;jbalkind@cs.princeton.edu&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Move fdt fixup helper routines to a different file</title>
<updated>2020-03-24T08:00:32Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-03-23T19:48:58Z</published>
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<id>urn:sha1:040e4e2ec220403fb2508aa0809052924ef63a0b</id>
<content type='text'>
FDT helper file contain both fdt fixup and parsing functions.

Split the fixup related functions to a separate file for a better code
organization.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Add OpenPiton platform support</title>
<updated>2020-03-24T07:48:38Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-03-23T19:48:56Z</published>
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<id>urn:sha1:fb84879e66bc5a26241bcf0472688851f7240acb</id>
<content type='text'>
OpenPiton is a research platform from Princeton University [1].

"OpenPiton is the world's first open source, general purpose,
multithreaded manycore processor. It is a tiled manycore
framework scalable from one to 1/2 billion cores."

Add OpenSBI support for OpenPiton. As it is based on ariane core,
it reuses the platform code from arine project.

[1]. https://github.com/PrincetonUniversity/openpiton

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: fpga/ariane: Remove redundant plic address macros</title>
<updated>2020-03-24T07:45:52Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-03-23T19:48:55Z</published>
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<id>urn:sha1:ed265b4498cabdcdeb24f5f76548b9df73ae07f8</id>
<content type='text'>
All the common PLIC specific macros are already defined in plic.c.

Remove it from platform code. While at it, Fix the other coding style
issues.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Move ariane standalone fpga project to its own project</title>
<updated>2020-03-24T07:42:17Z</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2020-03-23T19:48:54Z</published>
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<id>urn:sha1:59688948421deea18993836152af66765bdc76f6</id>
<content type='text'>
Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: sifive/fu540: Remove FU540_ENABLED_HART_MASK option</title>
<updated>2020-03-19T04:02:45Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-16T04:59:34Z</published>
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<id>urn:sha1:315a87710fd16009ad709445d5cf55cc6cca2e69</id>
<content type='text'>
The FU540_ENABLED_HART_MASK compile time option was added for initial
bring-up on SiFive Unleashed. This option is redundant now because
disabled_hart_mask is already removed. Based on this rationale, we
remove FU540_ENABLED_HART_MASK compile time option.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: sbi_platform: Introduce HART index to HART id table</title>
<updated>2020-03-19T04:00:01Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-03-15T06:09:25Z</published>
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<id>urn:sha1:c51f02cf143b081c2a81717393a0e6cef2ce2521</id>
<content type='text'>
A platform can have discontinuous and/or sparse HART ids so we
cannot always assume a set of HARTs with continuous HART ids.

This patch adds support for discontinuous and sparse HART ids by
introducing HART index to HART id table. This table has platform
hart_count entries and it maps HART index to HART id.

The HART index to HART id table has only two restrictions:
1. HART index &lt; sbi_platform hart_count
2. HART id &lt; SBI_HARTMASK_MAX_BITS

Example1:
Let's say we have a platform with 2 HART ids 11 and 22, for such a
a platform:
hart_count = 2
hart_index2id[0] = 11
hart_index2id[1] = 22

Example2:
Let's say we have a platform with 5 HARTs ids 0, 1, 2, 3, and 4
but out of these HART with id 0 is not usable so for such a platform:
hart_count = 5
hart_index2id[0] = -1U
hart_index2id[1] = 1
hart_index2id[2] = 2
hart_index2id[3] = 3
hart_index2id[4] = 4
OR
hart_count = 4
hart_index2id[0] = 1
hart_index2id[1] = 2
hart_index2id[2] = 3
hart_index2id[3] = 4

With HART index to HART id table in place, the hart_disabled()
callback is now redundant so we remove it as well.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Update to call general DT fix-up helper</title>
<updated>2020-03-18T05:39:31Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2020-03-17T14:59:51Z</published>
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<id>urn:sha1:3f8d754c2c7f2937b10013ea2866d7e7ebfee60b</id>
<content type='text'>
Platform andes/ae350, ariane-fpga, qemu/virt and sifive/fu540 codes
have been updated to call this general DT fix-up helper.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: sifive/fu540: Replace cpu0 node fix-up with the new helper</title>
<updated>2020-03-18T05:26:43Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2020-03-17T14:59:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=3f1c847d1fec852a2b98ee408e4193d70949acd4'/>
<id>urn:sha1:3f1c847d1fec852a2b98ee408e4193d70949acd4</id>
<content type='text'>
This replaces the FU540 specific cpu0 node "status" property fix-up
with the newly introduced generic fdt_cpu_fixup() helper.

Unlike previous logic, the helper routine does not test the "mmu-type"
property to determine which node we should fix up, instead it uses
sbi_platform_hart_disabled() API.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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