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<title>opensbi.git/platform, branch v1.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/platform?h=v1.2</id>
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<updated>2022-12-17T03:33:30Z</updated>
<entry>
<title>lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers</title>
<updated>2022-12-17T03:33:30Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-11T06:54:24Z</published>
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<id>urn:sha1:9a2eeb4aaeac9102a7db3676035d83394784c88b</id>
<content type='text'>
Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers</title>
<updated>2022-12-17T03:30:29Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-11T06:54:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8509e46ca63a4ed7dff2244cd7f288bf5591ab61'/>
<id>urn:sha1:8509e46ca63a4ed7dff2244cd7f288bf5591ab61</id>
<content type='text'>
Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Add Renesas RZ/Five initial support</title>
<updated>2022-12-12T13:20:56Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:10Z</published>
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<id>urn:sha1:8b1617d13a4200d1ec7d1604e4a4025cc1bcf891</id>
<content type='text'>
This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Make use of fdt_match_node()</title>
<updated>2022-12-09T05:43:00Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-07T16:14:19Z</published>
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<id>urn:sha1:ed8b8f5254752b1a7c7b90f61302095eade5b04a</id>
<content type='text'>
It makes sense to use fdt_match_node() instead of fdt_find_match()
in fw_platform_lookup_special() as we already have the start offset
to search from.

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic/andes: Enable generic platform support for AE350</title>
<updated>2022-12-05T11:54:32Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-12-05T02:03:57Z</published>
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<id>urn:sha1:a36d455182ea0e34d7372110fea215c74f747da2</id>
<content type='text'>
We move andes directory to platform/generic as the necessary fdt
drivers are available, the users can enable the console, timer, ipi,
irqchip and reset devices by adding device tree nodes stated in the
docs/platform/andes-ae350.md.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic/allwinner: Remove ghostly type cast</title>
<updated>2022-12-04T15:08:46Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2022-11-19T08:55:07Z</published>
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<id>urn:sha1:9a740f5c4655053f4d8c7df65f51ad58cfb1bb2e</id>
<content type='text'>
Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init
to be u32 for a while and u64 for a while.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic/allwinner: Remove unused header files</title>
<updated>2022-11-22T06:16:19Z</updated>
<author>
<name>Leizheng Zhang</name>
<email>zhangleizheng@eswincomputing.com</email>
</author>
<published>2022-11-18T05:20:29Z</published>
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<id>urn:sha1:1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e</id>
<content type='text'>
Remove "#include &lt;sbi/sbi_console.h&gt;"

Signed-off-by: Leizheng Zhang &lt;zhangleizheng@eswincomputing.com&gt;
Reviewed-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>platform: andes/ae350: Add AE350 domain support</title>
<updated>2022-10-23T05:05:00Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:51Z</published>
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<id>urn:sha1:c8683c57f62c00e84ea66a5354a29ffcfec2a9eb</id>
<content type='text'>
Add domains_init platform hook for Andes AE350, users can add domain
description in device tree and select FDT domain support in Kconfig
to achieve system-level partitioning.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Add Andes fdt ipi driver support</title>
<updated>2022-10-23T05:01:01Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:50Z</published>
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<id>urn:sha1:ce7c490719ed4e268979c8b6b54a5252396fbb3b</id>
<content type='text'>
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.

Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.

dts example (Quad-core AX45MP):

  plicsw: interrupt-controller@e6400000 {
          compatible = "andestech,plicsw";
          reg = &lt;0x00000000 0xe6400000 0x00000000 0x00400000&gt;;
          interrupts-extended = &lt;&amp;CPU0_intc 3
                                 &amp;CPU1_intc 3
                                 &amp;CPU2_intc 3
                                 &amp;CPU3_intc 3&gt;;
          interrupt-controller;
          #address-cells = &lt;2&gt;;
          #interrupt-cells = &lt;2&gt;;
  };

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: andes/ae350: Add fw_platform_init for platform initialization</title>
<updated>2022-10-23T05:00:21Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:49Z</published>
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<id>urn:sha1:6f3258e67187554b1202d3d2a065ef1adcdde3e6</id>
<content type='text'>
This patch adds fw_platform_init() to initialize ae350 platform.name
and platform.hart_count by parsing device tree.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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