opensbi.git/platform, branch v1.4

lib: sbi: Allow ecall handlers to directly update register state

2023-12-19T10:26:37Z

Some of the upcoming SBI extensions (such as SSE) will directly update register state so improve the prototype of ecall handler to accommodate this. Further, this flexibility allows us to push the trap redirection from sbi_ecall_handler() to the sbi_ecall_legacy_handler(). Signed-off-by: Anup Patel

lib: utils/irqchip: Add shared MMIO region for PLIC in root domain

2023-12-19T10:26:37Z

On platforms with Smepmp, the MMIO regions accessed by M-mode need to be explicitly marked with M-mode only read/write or shared (both (M-mode and S-mode) read/write permission. If the above is not done then runtime PLIC access from M-mode on platforms with Smepmp will result in access fault when further results in CPU hotplug not working. Signed-off-by: Anup Patel

platform: generic: Fine tune fw_platform_calculate_heap_size()

2023-12-19T10:26:37Z

Let's use SBI_TLB_INFO_SIZE instead of hard-coded 0x40 in fw_platform_calculate_heap_size() to fine tune the heap size required for per-hart TLB fifos. Signed-off-by: Anup Patel

platform: recalculate heap size to support new tlb entry number

2023-12-11T03:53:24Z

Previous patch introduced a change that using hart count as the default number of tlb entries in the fifo. This makes the default tlb fifo size grow in square with the number of harts. So the default heap size is not enough to allocate tlb fifo when the hart count is big. Fixes: 52fd64b ("platform: Uses hart count as the default size of tlb info") Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: andes: Factor out is_andes() helper

2023-12-06T12:33:12Z

We will need is_andes(45) in the following patch, so factor out the code that parses marchid to make it reusable for checking any Andes CPU variants. Also improves the comment in ae350_hart_start(). Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: rzfive: Enable Andes PMU for RZ/Five

2023-12-06T12:27:28Z

Enable Andes PMU extension support for RZ/Five. We also staticize renesas_rzfive_early_init() as it is not used outside of this unit. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: andes: Enable Andes PMU for AE350

2023-12-06T12:25:55Z

Enable Andes PMU extension support for AE350 platforms. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: andes: Add Andes custom PMU support

2023-12-06T12:23:45Z

Before the ratification of Sscofpmf, the Andes PMU extension was designed to support the sampling and filtering with hardware performance counters (zihpm), it works with the current SBI PMU extension and Linux SBI PMU driver. We implement 1) the PMU device callbacks that update the corresponding bits on custom CSRs, 2) extentions_init() to detect the hardware support of Andes PMU and initialize the per-hart PMU related CSR, and 3) pmu_init() to register PMU device and populate event mappings. Also define a andes_pmu_setup() function which is in preparation for adding default PMU mappings in andes_hpm.h Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel

platform: generic: Introduce pmu_init() platform override

2023-12-06T12:19:59Z

Add pmu_init() platform override, which will be used to register PMU device and populate event mappings. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: include: andes45: Add PMU related CSR defines

2023-12-06T12:01:36Z

Add CSR definitions for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar