opensbi.git/platform, branch v1.8

platform: generic: eswin: Add shutdown/reboot support for Hifive Premier P550

2025-12-21T15:32:46Z

Hifive Premier P550[1] is a Mini-DTX form factor board with EIC7700X. It has a STM32F407VET6 onboard MCU acting as the BMC, controlling ATX power on/off while providing remote management features. The EIC7700X SoC/SoM communicates with the BMC via UART2, using ESWIN's protocol. The messages transmitted are fixed sizes (267 bytes), and depending on the type, can be directional or bi-directional. The shutdown and cold reboot requests are directional messages from SoC to BMC (NOTIFY type) with CMD_POWER_OFF or CMD_RESTART. The payload of shutdown/cold reboot requests should be empty and are ignored by the BMC at the moment. A HFP (Hifive Premier) specific reset device is registered in addition to the SoC reset device. For shutdown and cold reboot, the board-level reset takes precedence. The definitions of the SoC <-> BMC message protocol is taken from ESWIN's repo [2]. The only file used from that repo is `hf_common.h` It's disjunctively dual licensed as (GPL-2.0-only OR BSD-2-Clause), hence, compatible with the license of OpenSBI. It's heavily modified and renamed as platform/generic/include/eswin/hfp.h. The author and copyright in the original file are retained. Validated shutdown/cold reboot working on Hifive Premier P550. [1] https://www.sifive.com/boards/hifive-premier-p550#documentation [2] https://github.com/eswincomputing/hifive-premier-p550-mcu-patches.git Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-8-ganboing@gmail.com Signed-off-by: Anup Patel

platform: generic: eswin: add EIC7700

2025-12-21T15:32:22Z

Initial platform support for ESWIN Computing EIC7700 based on public SoC datasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots fine, and I've tested Geekbench 6.5.0 Preview and got scores on par with the vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and other boards will be implemented in subsequent commits. At this point, only SoC-level warm reset is implemented. The files and functions are intentionally named as eic770x in many places for future enhancements to support the 2 die version of the same SoC, namely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only deals with the single die version, and the assumption is we can be either die with id=0 or id=1, but there's only a single die in the system, or we are only using a single die out of 2. However, the way the SoC handles 2- die greatly affects how we configure it in a 1-die setup. EIC770X address map has die 0/1 memory regions interleaved (see comments in eic770x.c). If only 1 die is connected or active, it creates holes in the address map for those regions corresponding to the remote die. When speculative- execution or HW prefetcher touches data-cacheable regions that happen to fall into those holes, it can trigger bus error. Specifically: - Remote (non-existent) die L3 zero device - Remote (non-existent) die cached memory region - Other holes in Memory Port To make matters worse, EIC770X doesn't have cache coherent DMA, and due to the fact that the P550 core lacks Svpbmt, the SoC maps main memory twice as different regions, so it can bypass cache and fetch the data directly from memory. In address space, we have two memory regions, one as cached, the other as uncached. Thus, we also need an extra PMP entry to protect OpenSBI blob from the uncached window. To do this, platform code requires single_fw_region, otherwise, we'll run out of PMP entries. EIC770X also have several feature disable/enable CSRs accessible in M mode. By default many core features such as speculation and HW prefetch are disabled, and M mode software is responsible of enabling. Hence, introduce 4 new build time tunable parameters to Kconfig, which reflects the values get updated to those CSRs: - ESWIN_EIC770X_FEAT0_CFG - ESWIN_EIC770X_FEAT1_CFG - ESWIN_EIC770X_L1_HWPF_CFG - ESWIN_EIC770X_L2_HWPF_CFG The default values are somewhat optimal for generic workloads. They are dumped when running SiFive's vendor OpenSBI, and in addition, with my own tuning to address the perf regression reported by drmpeg [3] To build the firmware+u-boot blob, Use the following, and docs [4] for testing it with UART boot without flashing: make FW_TEXT_START=0x80000000 \ FW_PAYLOAD_OFFSET=0x200000 \ FW_PAYLOAD_PATH=u-boot-nodtb.bin \ FW_PAYLOAD_FDT_ADDR=0xf8000000 \ FW_FDT_PATH=u-boot.dtb [1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual [2] https://github.com/geerlingguy/sbc-reviews/issues/82 [3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15 [4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-6-ganboing@gmail.com Signed-off-by: Anup Patel

platform: generic: Keep some empty space in FDT passed to next stage

2025-12-16T14:44:08Z

Leaving no empty space in the FDT passed to the next booting stage causes the following U-Boot crash on Ventana internal platforms: Unhandled exception: Load access fault EPC: 00000000fffa6372 RA: 00000000fffa7418 TVAL: 0001746174730068 EPC: 0000000080245372 RA: 0000000080246418 reloc adjusted SP: 00000000fef38440 GP: 00000000fef40e60 TP: 0000000000000000 T0: 00000000fef40a70 T1: 000000000000ff00 T2: 0000000000000000 S0: 00000000fffc17a8 S1: 00000000fef38d40 A0: 7375746174730068 A1: 00000000fffc17a8 A2: 0000000000000010 A3: 0000000000000010 A4: 0000000000000000 A5: 00000000fffc17b8 A6: 0000000000ff0000 A7: 000000000000b100 S2: 0000000000000000 S3: 0000000000000001 S4: 00000000fef38d40 S5: 7375746174730068 S6: 0000000000000000 S7: 00000000fef4eef0 S8: 00000000fef4ef90 S9: 0000000000000000 S10: 0000000000000000 S11: 00000000fef4efc0 T3: 00000000fef40ea8 T4: 0000000000ff0000 T5: 00000000fef40a60 T6: 00000000fef40a6c To address the above issue, keep some minimal empty space in the FDT instead of no empty space. Fixes: bbe9a23060e9 ("platform: generic: Pack the FDT after applying fixups") Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209053130.407935-1-apatel@ventanamicro.com Signed-off-by: Anup Patel

platform: generic: spacemit: add missing objects.mk

2025-12-08T06:26:37Z

Add the missing objects.mk for the SpacemiT platform, required for the K1 platform to be included in the build. Fixes: 1f84ec2a ("platform: generic: spacemit: add K1") Signed-off-by: Junhui Liu Acked-by: Troy Mitchell Link: https://lore.kernel.org/r/20251124-k1-fix-v1-1-8d7e7a29379e@pigmoral.tech Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive Extensible Cache (EC) driver

2025-12-08T04:31:20Z

Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Co-developed-by: Yong-Xuan Wang Signed-off-by: Yong-Xuan Wang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive PL2 controller

2025-12-08T04:31:05Z

SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin Signed-off-by: Eric Lin Co-developed-by: Zong Li Signed-off-by: Zong Li Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel

platform: openpiton: use generic early init

2025-12-01T05:11:11Z

Add code for using generic_early_init so that the uart parameters are parsed from dtb. Signed-off-by: Manuel Hernández Méndez Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251107075429.1382-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel

platform: ariane: parse dtb for getting some initial parameters

2025-12-01T05:03:31Z

Add code for getting some uart, clint and plic parameters from device tree. Signed-off-by: Manuel Hernández Méndez Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251107075412.1350-1-manuel.hernandez@openchip.com Signed-off-by: Anup Patel

platform: ariane: Move ariane platform from fpga to generic

2025-11-05T15:52:41Z

The Ariane framework has a generic PMU that is not used by OpenSBI. Due to OpenSBI’s build system we cannot directly reuse the generic platform functions, so move the Ariane platform to generic. Also due to the generic platform is where new features are added. Signed-off-by: Manuel Hernández Méndez Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com Signed-off-by: Anup Patel

lib: utils: Add MPXY RPMI mailbox driver for performance

2025-11-04T05:05:59Z

Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel