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2020-02-19platform: qemu: virt: Correct the typo in config.mkBin Meng
It should be "aligned". Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-19platform: sifive: fu540: Add 32-bit specific fdt/payload addressesBin Meng
For testing 32-bit SiFive specific drivers with QEMU riscv32, add 32-bit specific FW_JUMP_FDT_ADDR and FW_PAYLOAD_OFFSET. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-19lib: Print interrupt and exception delegation in boot printsAnup Patel
We print MIDELEG and MEDELEG CSRs as part of boot prints so that boot log shows the interrupts and exceptions delegated to S-mode. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-19lib: Don't check MIDELEG and MEDELEG at end of delegate_traps()Anup Patel
The MIDELEG and MEDELEG CSR checks at end of delegate_traps() were added for initial bring-up on SiFive Unleashed and QEMU. These checks are not required any more and in-future these checks can cause failures because some of the MIDELEG/MEDELEG bits will be hard-wired to 0 or 1. For related discussion, refer github issue: https://github.com/riscv/opensbi/issues/157 Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-18lib: utils: htif: Fix 32-bit buildBin Meng
When building 32-bit OpenSBI images, we get: lib/utils/sys/htif.c: In function '__check_fromhost': lib/utils/sys/htif.c:12:31: error: left shift count >= width of type [-Werror=shift-count-overflow] #define HTIF_DATA_MASK ((1UL << HTIF_DATA_BITS) - 1) ^~ Fixes: c2f23cc6edd7 ("platform: Add Spike initial support") Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18Revert "lib: Use __builtin_ctzl() in pmp_get()"Anup Patel
This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel <[email protected]>
2020-02-18doc: thead-c910: Fix doc stylesBin Meng
- make title underline the same length as the title itself - satisfy the 80 character per line rule as much as possible Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: sifive_fu540: Fix doc stylesBin Meng
- make title underline the same length as the title itself - put all URLs at the end of the doc Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: qemu_virt: Fix doc stylesBin Meng
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: ariane-fpga: Fix doc stylesBin Meng
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - make title underline the same length as the title itself - remove the redundant FPGA (was FPGA FPGA SoC) Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: andes-ae350: Fix doc stylesBin Meng
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - remove unnecessary spaces between words Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: payload_linux: Fix doc stylesBin Meng
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18doc: coreboot: Fix doc stylesBin Meng
- put all URLs at the end of the doc - satisfy the 80 character per line rule as much as possible Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-18ThirdPartyNotices: Fix doc stylesBin Meng
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-17docs: platform: Add documentation for Spike platformAnup Patel
This patch adds documentation to build and run OpenSBI on Spike simulator and QEMU Spike machine. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]>
2020-02-17scripts: Add Spike to platform list of binary archive scriptAnup Patel
The Spike platform support works perfectly fine on QEMU RV64 Spike machine and Spike emulator. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]>
2020-02-17platform: Remove stale options from config.mk filesAnup Patel
This patch removes stale options from config.mk files of Ariane FPGA and QEMU virt platform support. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-17platform: Add Spike initial supportJames Clarke
This patch adds initial platform support Spike emulator. Signed-off-by: James Clarke <[email protected]> Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-13lib: irqchip/plic: Disable all contexts and IRQsAtish Patra
To initialize PLIC in sane state, we should: 1. set maximum threshold value of M-mode PLIC contexts 2. set maximum threshold value of S-mode PLIC contexts 3. set irq priorities to miniumum Fix the comment and initialize the threshold/priorities correctly. Signed-off-by: Anup Patel <[email protected]> Signed-off-by: Atish Patra <[email protected]>
2020-02-13lib: Initialize out value in SBI callsAtish Patra
As per the SBI specification, the return value in sbiret is undefined if not explicitly described in the function. However, supervisor may check this value by mistake and get a garbage value. Initialize it to zero to avoid nasty supervisor bugs. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-13lib: Use __builtin_ctzl() in pmp_get()Li Jinpei
We should should __builtin_ctzl() in pmp_get() instead of custom ctz() function. Signed-off-by: Li Jinpei <[email protected]> Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-13lib: sbi_scratch: use bitwise ops in sbi_scratch_alloc_offset()Li Jinpei
Instead of using loop to make "size" machine word aligned, we should use bitwise ops. Signed-off-by: Li Jinpei <[email protected]> Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-11doc: sifive: fu540: Update QEMU instruction when using U-Boot as the payloadBin Meng
Document that when U-Boot v2020.01 (or higher) is used as the payload, we need adjust the instructions a little bit when testing OpenSBI with QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-02-07platform: sifive: fu540: Add platform specific 'make run' cmdBin Meng
This adds sifive/fu540 specific QEMU run command. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-07platform: Drop qemu/sifive_u supportBin Meng
With QEMU v4.2 RISC-V changes to improve the emulation fidelity of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10 / Linux kernel v5.3 images built for the SiFive HiFive Unleashed board can be used out of the box without any special hack. Hence there is no need for us to continue supporting such a special target in OpenSBI. Going forward, sifive/fu540 platform can be used on both real hardware and QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-06makefile: add support for building on macOSAlex Richardson
On macOS the readlink command does not include a -f flag. Instead default to using GNU readlink (which is often installed as greadlink). Signed-off-by: Alex Richardson <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2020-02-05platform: sifive/fu540: Set tlb range flush limit to zeroAtish Patra
It was reported that tlb range flush is not working on fu540. Only tlb full flush seems to work on fu540 probably due to some hardware errata. Set the tlb flush limit to zero so that all tlb flush requests are converted to full flush. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-02-05platform: Add an platform ops to return platform specific tlb flush limitAtish Patra
If a platform requires to perform a tlb full flush, they should set the tlb_range_flush_limit value to zero. However, corresponding platform API ignore the value and continue to return the default value. Add a platform ops to retrieve platform specific tlb range flush limit. The platform variable becomes redundant in presence of the platform ops. Take this opportunity to remove the variable as well. The default is still set to smallest page size in RISC-V (4KB), as there is no way to figure out a best value for all platforms. Individual platform should set it to the optimal value for their platform. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-25platform: Update UART base addresses for qemu/sifve_uNikita Ermakov
In the QEMU [1] there was a change of the UART base addresses for sifive_u machine to match the hardware. Make corresponding changes in the opensbi for qemu/sifive_u platform. [1] https://git.qemu.org/?p=qemu.git;a=commitdiff;h=4b55bc2b5f7ff065da5d2b813ee5153c598d3764 Signed-off-by: Nikita Ermakov <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-24platform: template: typo fix in system reboot/shutdown namesJiuyang Liu (Sequencer)
This patch does minor typo fix in system reboot/shutdown names in platform operations. Signed-off-by: Jiuyang Liu (Sequencer) <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Signed-off-by: Anup Patel <[email protected]>
2020-01-22lib: Factor-out SBI base extensionAnup Patel
This patch factor-out SBI base extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Factor-out SBI vendor extensionAnup Patel
This patch factor-out SBI vendor extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Factor-out SBI replacement extensionsAnup Patel
This patch factor-out SBI replacement extensions (such as RFENCE, IPI, and TIME) into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Factor-out SBI legacy extensionAnup Patel
This patch factor-out SBI legacy extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Add dynamic registration of SBI extensionsAnup Patel
This patch extends our SBI ecall implementation to allow dynamic registration of various SBI extensions. Using this dynamic registration we can break-up SBI ecall implementation into multiple files and even register experimental/custom SBI extensions from platform code. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22include: Add generic and simple list handling APIsAnup Patel
This patch adds generic and simple list handling APIs adapted from Xvisor sources. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Initialize TLB management directly from coldboot/warmboot pathAnup Patel
Currently, the remote TLB management is initialized via IPI init which is counter intuitive. This patch initializes remote TLB management directly from init_coldboot() and init_warmboot() after IPI init is done. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Drop _fifo from the name of various sbi_tlb_fifo_xyz() functionsAnup Patel
This patch drops _fifo from the name of various sbi_tlb_fifo_xyz() functions because all these functions deal with remote TLB managment and FIFO is the per-HART data structure used internally by remote TLB implementation. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Introduce sbi_ipi_event_create/destroy() APIsAnup Patel
This patch introduces sbi_ipi_event_create/destroy() APIs and struct sbi_ipi_event_ops for creating/destroying IPI events at runtime based of event operations. This new APIs will help platform code and utils code to create custom IPI events which are not part of generic OpenSBI library. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Introduce sbi_tlb_fifo_request() APIAnup Patel
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_tlb_fifo_request() for halting a set of HARTs. This way in future we can assign any IPI event number for remote FENCE within sbi_tlb.c only. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Introduce sbi_ipi_send_halt() APIAnup Patel
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_halt() for halting a set of HARTs. This way in future we can assign any IPI event number for HART halting within sbi_ipi.c only. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Introduce sbi_ipi_send_smode() APIAnup Patel
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_smode() for injecting S-mode software interrupts. This way in future we can assign any IPI event number for S-mode IPIs within sbi_ipi.c only. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22lib: Move struct sbi_ipi_data definition to sbi_ipi.cAnup Patel
The struct sbi_ipi_data is only used in sbi_ipi.c so move it to sbi_ipi.c from sbi_ipi.h. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-22include: Typo fix in comment for SBI_SCRATCH_SIZE defineAnup Patel
This patch fixes a minor typo in comment for SBI_SCRATCH_SIZE define. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-01-20scripts: Add C910 to platform list in the binary archive scriptLiu Yibin
This patch adds T-HEAD C910 to RV64 platform list in the binary archive script. Signed-off-by: Liu Yibin <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-15platform: thead/c910: Don't set plic/clint address in warm bootLiu Yibin
Since all harts share the same plic/clint address now, setting them during cold boot is just fine. Signed-off-by: Liu Yibin <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-15platform: thead/c910: Don't enable L2 cache in warm bootLiu Yibin
Since all harts share the same L2 cache now, there's no need to Enable L2 cache in warm boot. Signed-off-by: Liu Yibin <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-10firmware: Fix placement of .align directivesAndreas Schwab
Move the .align directives after switching the section. We want to align the start of the current section, not the end of the previous section. This also obsoletes the misguided workaround of disabling relaxation. Signed-off-by: Andreas Schwab <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2020-01-10docs: platform: Update SiFive FU540 doc as-per U-Boot v2020.01Anup Patel
With U-Boot v2020.01, the SiFive FU540 DTB required by U-Boot is embedded in U-Boot binary itself so we don't need to do anything special for U-Boot v2020.01 as payload to OpenSBI firmware. This patch updates SiFive FU540 documenation assuming we use latest U-Boot v2020.01 release. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]>
2020-01-09platform: thead/c910: Remove SBI_PLATFORM_HAS_PMPLiu Yibin
T-head c910 is a generic FPGA platform so we cannot define PMP configuration for it in OpenSBI because PMP configuration tend to be SOC specific. Signed-off-by: Liu Yibin <[email protected]> Reviewed-by: Atish Patra <[email protected]>
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