summaryrefslogtreecommitdiff
path: root/include/sbi/riscv_encoding.h
AgeCommit message (Collapse)Author
2023-02-27lib: sbi_hart: Enable hcontext and scontextNylon Chen
According to the description in "riscv-state-enable[0]", to access h/scontext in S-Mode, we need to enable the 57th bit. If it is not enabled, an "illegal instruction" error will occur. Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0] Signed-off-by: Nylon Chen <[email protected]> Reviewed-by: Zong Li <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-09-01include: Remove sideleg and sedelegRahul Pathak
sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-08-22include: Add mstatus[h].GVA encodingsVivian Wang
The machine mode GVA field is in mstatus for RV64 and mstatush for RV32, and is available if the hypervisor extension is available. If an exception occurs, we may need to redirect the trap to HS-mode, in which case, hstatus.GVA should be set to same as the machine mode GVA bit. Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT encodings. The SHIFT index is helpful in assembly code, since field extraction can be implemented in only one register. In pseudocode: - For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1; - For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1; Signed-off-by: Vivian Wang <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-06-21lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2022-06-21include: sbi: Add mtinst/htinst psuedoinstructionsdramforever
Add psuedoinstruction encodings written to mtinst/htinst for faults caused by implicit memory access for VS-stage address translation Signed-off-by: dramforever <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-06-01lib: sbi_illegal_insn: Add emulation for fence.tsoSamuel Holland
While OpenC906 appears to properly decode `fence.tso` as a fence instruction[1], the version of the C906 taped out in the Allwinner D1 does not, and raises illegal instruction. Handle this errata by emulating `fence.tso` as `fence rw, rw`. [1]: https://github.com/T-head-Semi/openc906/blob/30827e7f/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L2097 Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-04-28lib: sbi: Implement Sstc extensionAtish Patra
Recently, Sstc extension was ratified. It defines stimecmp which allows the supervisor mode to directly update the timecmp value without the need of the SBI call. The hardware also can inject the S-mode timer interrupt direclty to the supervisor without going through the M-mode. To maintain backward compatibility with the older software, SBI call now uses stimecmp directly if the hardware supports. Implement the Sstc extension. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-04-17include: correct the definition of MSTATUS_VSVincent Chen
Accordind to the RISC-V privileged specification, the VS filed is mstatus[10:9] instead of mstatus[24:23]. Modify the MSTATUS_VS to the correct value. Reported-by: I-Cheng Cheng <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Reviewed-by: Xiang W <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-04-11lib: sbi: Add Smstateen extension definesMayuresh Chitale
Smstateen extension provides a mechanism to plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Xiang W <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2022-04-05include: Add defines for [m|h|s]envcfg CSRsAnup Patel
The latest RISC-V privileged specification introduces xenvcfg CSRs to enable/disable certain features/extensions for lower privilege modes. This patch adds defines for these new [m|h|s]envcfg CSRs. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]> Reviewed-by: Xiang W <[email protected]>
2022-02-15include: sbi: Add AIA related CSR definesAnup Patel
The RISC-V AIA specification improves handling of per-HART local interrupts in a backward compatible manner. This patch adds defines for the new RISC-V AIA CSRs. Signed-off-by: Anup Patel <[email protected]> Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2022-02-04lib: sbi: Disable interrupt during config matchingAtish Patra
PMU overflow interrupt should be disabled durinig initial configuration of counters. They should be enabled while starting counters. Fixes: 730f01bb41a6 ("lib: sbi: Support sscofpmf extension in OpenSBI") Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2021-11-11lib: sbi: Support sscofpmf extension in OpenSBIAtish Patra
This patch adds sscofpmf extension in pmu module which includes following things. 1. Enable overflow irq when starting a counter. 2. Setting the correct event filters passed from supervisor. 3. Delegating the overflow interrupt to the supervisor. 4. Add RV32 support for sscofpmf. Reviewed-by: Anup Patel <[email protected]> Reviewed-by: Bin Meng <[email protected]> Signed-off-by: Atish Patra <[email protected]>
2021-11-11lib: sbi: Delegate PMU counter overflow interrupt to S modeAtish Patra
OpenSBI doesn't handle PMU counters for now. Delegate the overflow counter to S-mode always. Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Atish Patra <[email protected]>
2021-11-11riscv: Add new CSRs introduced by Sscofpmf[1] extensionAtish Patra
[1] https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view Reviewed-by: Xiang W <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Atish Patra <[email protected]>
2020-09-09include: Rename ECALL defines to match latest RISC-V specAnup Patel
We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-09-01include: sbi: Few cosmetic changes in riscv_encoding.hAnup Patel
This patch does following cosmentic changes to riscv_encoding.h: 1. Re-organize CSR defines to match CSR listing in latest RISC-V privilege spec 2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-09-01lib: sbi: Improve PMP CSR detection and progammingAnup Patel
As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-06-08lib: Add RISC-V hypervisor v0.6.1 supportAnup Patel
To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-05-07lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementationAnup Patel
The HFENCE VVMA instructions flushes TLB based on the VMID present in HGATP CSR. To handle this, we get the current VMID for SBI HFENCE VVMA call and we use this current VMID to do remote TLB HFENCE VVMA on desired set of HARTs. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-05-07include: sbi: Remove redundant page table related definesAnup Patel
We don't have page table programming in OpenSBI so let's remove redundant page table related defines from riscv_encoding.h. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2020-04-17lib: Support vector extensionAtish Patra
Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Anup Patel <[email protected]>
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <[email protected]>
2019-12-16include: Add guest external interrupt related definesAnup Patel
With RISC-V H-extension v0.5 draft, we have special support for guest external interrupts so this patch adds related defines which were missed-out previously. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Alistair Francis <[email protected]>
2019-11-06include: Use _UL() and _ULL() for defines in riscv_encoding.hAnup Patel
The riscv_encoding.h is shared with assembly sources so we use _UL() and _ULL() for register fields related defines. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2019-11-06include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draftAnup Patel
This patch sync-up encoding header with the latest privilege specifications draft v1.12 and hypervisor specifications draft v0.5. The MSTATUS.MTL and HSTATUS.STL bits are not present anymore and will be removed by another patch series for hypervisor v0.5-draft. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>
2019-09-30lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSRAnup Patel
For platforms not having TIME CSR, we trap-n-emulate TIME CSR read/write in OpenSBI. Same rationale applies to HTIMEDELTA CSR as well so we trap-n-emulate HTIMEDELTA CSR for platforms not having TIME CSR. Signed-off-by: Anup Patel <[email protected]>
2019-09-30lib: Redirect WFI trapped from VS/VU mode to HS-modeAnup Patel
The WFI will trap as illegal instruction trap when executed in VS/VU mode so we just forward/redirect it to HS-mode so that hypervisor can deal with it appropriately. Signed-off-by: Anup Patel <[email protected]>
2019-09-30lib: Extend sbi_trap_redirect() for hypervisor extensionAnup Patel
When hypervisor extension is available, we can get traps from VS/VU modes. We should be able to force redirect some of these traps to HS-mode. In other words, we should be able forward traps from VS/VU mode to HS-mode using sbi_trap_redirect() hence this patch. Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Anup Patel <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
2019-09-30lib: Extend sbi_hart_switch_mode() to support hypervisor extensionAnup Patel
This patch extends sbi_hart_switch_mode() to support entering VS/VU modes when hypervisor extension is available. Signed-off-by: Anup Patel <[email protected]>
2019-04-24all: Annotate some tables to have clang-format leave them aloneOlof Johansson
One of the shortcomings of clang-format is that it doesn't allow for aligned define tables, which is used for a number of constants. Add annotation to disable the automatic formatting where needed. Signed-off-by: Olof Johansson <[email protected]>
2019-04-06lib: Fix the ecall macro definitionsAlistair Francis
Fix the ECALL definitions to matc the latest information in the privlidge spec table 5.5. Signed-off-by: Alistair Francis <[email protected]>
2019-02-14lib: Use CSR_<FOO> instead of <foo> for csr_*()Atish Patra
Some older toolchains may not have all the csr's defined. Update all the csr functions to use the CSR_ #define values instead of the toolchain defined values. Suggested-by: Olof Johansson <[email protected]> Signed-off-by: Atish Patra <[email protected]>
2019-01-24all: Update copyright header in all filesAnup patel
This patch updates copyright header in all files as follows: 1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line 2. Change copyright year to 2019 for Western Digital Signed-off-by: Anup Patel <[email protected]>
2019-01-03include: Add hard FP access macros and definesAnup Patel
This patch adds hardware floating-point (hard FP) access macros and defines. Signed-off-by: Anup Patel <[email protected]>
2018-12-31lib: Redirect illegal instruction trap to S-mode when not handledAnup Patel
Currently, we fail with error SBI_ENOTSUPP when we are not able to handle illegal instruction trap. Instead, we should just redirect illegal instruction trap to S-mode when not handled. This redirection of illegal instruction trap will help lazy save/restore of floating point registers to work correctly in Linux kernel. Signed-off-by: Anup Patel <[email protected]>
2018-12-26lib: Move instruction encoding macros to riscv_encoding.hAnup Patel
This patch moves all instruction encoding macros to riscv_encoding.h. Signed-off-by: Anup Patel <[email protected]>
2018-12-11Initial commit.Anup Patel
Signed-off-by: Anup Patel <[email protected]>
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-02 19:09:27 +0000