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The sbi_hart_pmp_get() and sbi_hart_pmp_check_addr() functions
are not used anymore hence this patch removes these functions.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_hsm_hart_start() should consider the domain under which we
are trying to start the HART. This will help ensure that HART A can
start HART B only if both HARTs A and B belong to the same domain.
We also have a special case when we bring-up boot HART of non-root
domains in sbi_domain_finalize() where we should skip domain checks
in sbi_hsm_hart_start(). To achieve this, sbi_hsm_hart_start() should
do domain checks only when domain parameter is non-NULL.
This patch extends sbi_hsm_hart_start() as-per above.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_hsm_hart_started_mask() API should take one more parameter
to allow caller specify domain under which started_mask is being
generated. Further, the sbi_hsm_hart_started_mask() depends on
sbi_hsm_hart_get_state() which also should return HART state under
specified domain.
This patch updates both sbi_hsm_hart_started_mask() and
sbi_hsm_hart_get_state() as-per above.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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An OpenSBI domain is a logical entity representing a set of HARTs
and a set of memory regions for these HARTs.
The OpenSBI domains support will allow OpenSBI platforms and previous
booting stage (i.e. U-Boot SPL, Coreboot, etc) to partition a system
into multiple domains where each domain will run it's own software.
For inter-domain isolation, OpenSBI will eventually use various HW
features such as PMP, ePMP, IOPMP, SiFive shield, etc but initial
implementation only use HW PMP support.
This patch provides initial implementation of OpenSBI domains where
we have a root/default domain and OpenSBI platforms can provide
non-root/custom domains using domain_get() callback.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_hartmask_test_hart() does not modify hartmask so the
hartmask pointer parameter should be declared const.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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The hartid parameter of sbi_hart_init() is not used anywhere in
sbi_hart_init() implementation so let's remove it.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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We factor-out PMP configuration from sbi_hart_init() as a separate
sbi_hart_pmp_configure() function and do the PMP configuration very
late in coldboot and warmboot path just before platform_final_init().
Eventually, this enable us to configure PMP totally based on OpenSBI
domain where OpenSBI domains can be parsed from device-tree in any of
the platform operations except platform_final_init().
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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The pmp_region_xyz() callbacks are not required in sbi_platform_operations
because we will be using OpenSBI domain memory regions to program the
PMP CSRs.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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The sbi_ecall.h and sbi_trap.h are not required to be included in
sbi_platform.h hence we remove it. This way sources requiring
these headers will have to explicitly include it thereby reducing
implicit includes.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
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%s/scatch/scratch
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We extend sbi_hart_pmp_check_addr() API so that users can specify
privilege mode of the address for checking PMP access permissions.
To achieve this, we end-up converting "unsigned long *size" parameter
to "unsigned long *log2len" for pmp_get() implementation so that we
can deal with regions of "1UL << __riscv_xlen" size in a special case
in sbi_hart_pmp_check_addr() implementation.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_scratch already has provision to specify the next stage mode
so we can leverage this to specify start mode to sbi_hsm_hart_start().
In future, this will be useful in providing SBI calls to U-mode on
embedded cores where we M-mode and U-mode but no S-mode.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and
CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that
it matches latest RISC-V privilege spec.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch does following cosmentic changes to riscv_encoding.h:
1. Re-organize CSR defines to match CSR listing in latest RISC-V
privilege spec
2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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A RISC-V platform can leave unimplemented MHPM counters hard-wired
to zero. We extend hart_detect_features() to detect MHPM counters
which are accessible and not hard-wired to zero. We also print
number of available MHPM counters as part of boot prints.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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As-per latest RISC-V privilege spec up to 64 PMP entries are supported.
Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR
fields are WARL and may be hardwired to zero.
This patch improves PMP CSR detection and progamming considering
above facts.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The SBI_HART_HAS_PMP feature is redundant because we already
have number of PMP regions returned by sbi_hart_pmp_count().
Checking whether PMP is supported for a HART can be simply done
by checking non-zero value returned by sbi_hart_pmp_count().
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This commit add an implementation of sbi_strncmp.
Signed-off-by: Abner Chang <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The value assigned to x by the shift assignment in the last if block of
ffs/fls is never read. Remove it.
Signed-off-by: Tobias Klauser <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This patch updates OpenSBI version to 0.8 as part of
release preparation.
Signed-off-by: Anup Patel <[email protected]>
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We should only return valid error codes from SBI ecalls as
defined by the RISC-V SBI spec.
To achieve this:
1. We use SBI_Exxxx defines for OpenSBI internal errors with
error values starting from -1000
2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
which are semantically same
4. We throw a error print and force return error code to
SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
error code being returned to S-mode
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
We add OpenSBI support for Shakti C-class SoC.
Signed-off-by: Vijai Kumar K <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This is achieved by removing the 'no-map' property from the
'reserved-memory' node when PMP is present, otherwise we keep it as it
offers a small protection if the OS does not map this region at all.
A new callback in platform_override is introduced and allows to fixup the
device-tree. It is used here to override this new default behaviour on
SiFive Fu540 platforms that has an erratum that prevents S-mode software
to access a PMP protected region using 1GB page table mapping.
If PMP is present, telling the OS not to map the reserved regions does not
add much protection since it only avoids access to regions that are already
protected by PMP. But by not allowing the OS to map those regions, it
creates holes in the OS system memory map and prevents the use of
hugepages which would generate, among other benefits, less TLB miss.
Signed-off-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.
Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.
We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add fdt_parse_clint_node() function which will be used by
fdt_ipi_clint and fdt_timer_clint drivers to parse CLINT details
from DT node.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We extend CLINT cold init function to have a "struct clint_data *"
parameter pointing to CLINT details. This allows platforms to use
CLINT functions for multiple CLINT instances.
When multiple CLINTs are present, the platform can also provide
one of the CLINT as reference CLINT for other CLINTs. This will
help CLINTs to sync their time value with reference CLINT using
a time_delta computed in warm init function.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We extend fdt_find_match() implementation by adding node offset
parameter which represents the first node to match from.
The improved fdt_find_match() can be used to find multiple
match nodes.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We extend all PLIC functions to have a "struct plic_data *"
parameter pointing to PLIC details. This allows platforms to
use these functions for multiple PLIC instances.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The "target_hart" and "hart_count" parameters of PLIC cold and
warm init functions are only used for sanity checks and not
required in PLIC initialization.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Cc: Abner Chang <[email protected]>
Signed-off-by: Daniel Schaefer <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.
Signed-off-by: Anup Patel <[email protected]>
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It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
are used.
2. This is consistent with lot of other APIs in sbi_hart.h
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We do following improvements for get_feature_str():
1. We should return "none" from get_feature_str() no features
available instead of sbi_boot_prints() explicitly handling
failure.
2. We don't need to return failure (just like misa_xlen())
because we are returning "none" for no features and we are
truncating output when space is not available.
3. Based on 1 and 2, the sbi_boot_prints() can be further
simplified.
4. No need for two char[] in sbi_boot_prints()
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print hart specific features in
a string format.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print platform features in a string
format. In the process, this patch moved relatively larger functions
to its own file from platform.h header file.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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As per the RISC-V specification, time value can be obtained from a time
CSR implemented in hardware or a MMIO based IP block. Qemu virt machine
already supports timer csr while CLINT provides the timer for other
platforms.
Implement a hart specific timer feature that can be detected at runtime.
As CSR based timer implementation are faster than MMIO address based, it
is always preferred over MMIO based one.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.
Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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There may be some features which are hart specific rather than a platform
specific feature. Add a framework to support that.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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There may be few common mathematics helper functions which can be used
anywhere in OpenSBI project.
Add a separate math helper function file to add these functions.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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As RISC-V ISA allows many CSRs such as pmp, s/mcounteren to be optional
in hardware, OpenSBI should provide an option to dynamically detect
these csr access capability at run time.
Implement a csr read/write access check helper macros.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.
Rename it to "expected" trap handler as it will be used in other cases in
future.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The RISC-V ISA string does not follow alphabetical order. Instead,
we have a RISC-V specific ordering of extensions in the RISC-V ISA
string. This patch improves misa_string() implementation to return
a valid RISC-V ISA string.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The HFENCE VVMA instructions flushes TLB based on the VMID
present in HGATP CSR. To handle this, we get the current
VMID for SBI HFENCE VVMA call and we use this current VMID
to do remote TLB HFENCE VVMA on desired set of HARTs.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We don't have page table programming in OpenSBI so let's remove
redundant page table related defines from riscv_encoding.h.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add simple reset framework which will select and use reset driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add simple serial framework which will select and use serial driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add simple irqchip framework which will select and use irqchip driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add simple ipi framework which will select and use ipi driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We add simple timer framework which will select and use timer driver
based on details in FDT passed by previous booting stage.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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