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The coldboot HART jumps to the next booting stage at the end of
init_coldboot() so it is absolutely necessary for coldboot HART
to support the privilege mode expected by the next booting stage.
We extend the coldboot HART selection in sbi_init() to ensure that
the selected coldboot HART always supports privilege mode specified
in scratch space (i.e. scratch->next_mode). This will further help
us allow E-core (without MMU) on SiFive Unleashed and PolarFire
ICICLE boards to proceed further and wait in HSM STOPPED state.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We extend sbi_hart_pmp_check_addr() API so that users can specify
privilege mode of the address for checking PMP access permissions.
To achieve this, we end-up converting "unsigned long *size" parameter
to "unsigned long *log2len" for pmp_get() implementation so that we
can deal with regions of "1UL << __riscv_xlen" size in a special case
in sbi_hart_pmp_check_addr() implementation.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_scratch already has provision to specify the next stage mode
so we can leverage this to specify start mode to sbi_hsm_hart_start().
In future, this will be useful in providing SBI calls to U-mode on
embedded cores where we M-mode and U-mode but no S-mode.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We should allow M-mode to M-mode ECALLs because:
1. No other mode can handle M-mode ECALLs
2. In future, we can allow M-mode baremetal application (not
linked to OpenSBI) running independently and cooperatively
without corrupting OpenSBI M-mode state (CSRs and memory).
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and
CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that
it matches latest RISC-V privilege spec.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The VS-mode ecall is supposed to be handled by HS-mode so
sbi_trap_handler() should fallback to default case for
VS-mode ecall trap.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We improve HPM CSR read/write emulation as follows:
1. Fail for unimplemented counters so that trap is redirected
to S-mode which can further help debugging S-mode software.
2. Check permissions in both MCOUNTEREN and SCOUNTEREN for
HS-mode and U-mode.
3. Don't check permissions for TIME CSR because we emulate
TIME CSR for both Host (HS/U-mode) and Guest (VS/VU-mode).
Also, faster TIME CSR read is very helpful for good
performance of S-mode software.
4. Don't emulate S-mode CSR read/write to M-mode HPM CSRs
because these should not be accessible to S-mode software.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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A RISC-V platform can leave unimplemented MHPM counters hard-wired
to zero. We extend hart_detect_features() to detect MHPM counters
which are accessible and not hard-wired to zero. We also print
number of available MHPM counters as part of boot prints.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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As-per latest RISC-V privilege spec up to 64 PMP entries are supported.
Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR
fields are WARL and may be hardwired to zero.
This patch improves PMP CSR detection and progamming considering
above facts.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The SBI_HART_HAS_PMP feature is redundant because we already
have number of PMP regions returned by sbi_hart_pmp_count().
Checking whether PMP is supported for a HART can be simply done
by checking non-zero value returned by sbi_hart_pmp_count().
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The Kendryte K210 follows RISC-V v1.9 spec so MTVAL has instruction
address (instead of instruction encoding) on illegal instruction trap.
To handle above case, we fix sbi_illegal_insn_handler() without any
impact on RISC-V v1.10 (or higher) systems. This achieved by exploiting
the fact that program counter (and instruction address) is always 2-byte
aligned in RISC-V world.
Signed-off-by: Anup Patel <[email protected]>
Tested-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We can have thundering hurd problem with coldboot_lock where the
boot HART can potentially starve trying to acquire coldboot_lock
because some of the non-boot HARTs are continuously acquiring and
releasing coldboot_lock. This can happen if MIP.MSIP bit is already
set for some of the non-boot HARTs.
To avoid thundering hurd problem for coldboot_lock, we use the
__smp_load_acquire() and __smp_store_release() for coldboot_done
flag and use coldboot_lock only for coldboot_wait_hmask.
Signed-off-by: Anup Patel <[email protected]>
Tested-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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When redirecting from VS/VU-mode to HS-mode, hstatus.SPVP was set
to the value of mstatus.SPP, as according to the specification both
flags should be set to the same value.
However, the assignment of SPVP takes place before SPP itself is
updated, which results in SPVP having an outdated value.
Signed-off-by: Georg Kotheimer <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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If MTINST[0:0] bit is 1 then we have transformed instruction encoding
in MTINST CSR. For transformed instructions, if the MTINST[1:1] bit
is Zero then original trapped instruction was a 16bit instruction
which was converted to 32bit instruction at time of taking trap.
We should use MTINST[1:1] bit to determine correct instruction length
of transformed instruction.
This patch updates misaligned load/store emulation as-per above.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This commit add an implementation of sbi_strncmp.
Signed-off-by: Abner Chang <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We should only return valid error codes from SBI ecalls as
defined by the RISC-V SBI spec.
To achieve this:
1. We use SBI_Exxxx defines for OpenSBI internal errors with
error values starting from -1000
2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
which are semantically same
4. We throw a error print and force return error code to
SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
error code being returned to S-mode
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in
function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift"
will go beyond "unsigned int" width. This patch tries to fix this issue.
In function 'pmp_get':
cfgmask = (0xff << pmpcfg_shift);
-->
cfgmask = (0xffUL << pmpcfg_shift);
In function 'pmp_set':
cfgmask = ~(0xff << pmpcfg_shift);
-->
cfgmask = ~(0xffUL << pmpcfg_shift);
Signed-off-by: Liush <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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If the platform doesn't support S-Mode don't print the delegation
registers.
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.
Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.
We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.
Signed-off-by: Anup Patel <[email protected]>
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This patch does few cosmetic improvements to HART feature detection:
1. Remove sbi_ perfix from HART feature detection functions
because all local/static functions in sbi_hart.c don't have
sbi_ prefix
2. Remove sbi_hart_set_feature() because it's quite small and
local/static in sbi_hart.c
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
are used.
2. This is consistent with lot of other APIs in sbi_hart.h
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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On platforms with continuous HART ids starting from zero:
0 <= boot HART id < platform HART count
The above co-relation of boot HART id and platform HART count
is true for most RISC-V platfors so it's better to print platform
HART count just before boot HART id.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We remove extra spaces from boot time prints.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We do following improvements for get_feature_str():
1. We should return "none" from get_feature_str() no features
available instead of sbi_boot_prints() explicitly handling
failure.
2. We don't need to return failure (just like misa_xlen())
because we are returning "none" for no features and we are
truncating output when space is not available.
3. Based on 1 and 2, the sbi_boot_prints() can be further
simplified.
4. No need for two char[] in sbi_boot_prints()
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We should detect HART features in sbi_hart_init() before
mstatus_init(), delegate_traps() and pmp_init().
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Currently, unprivileged access functions uses few additional instructions
which are redundant. It also uses specific registers which are not necessary.
Remove those additional instructions and let the compiler choose the
registers.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print hart specific features in
a string format.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We have now clear distinction between platform and hart features.
Modify the boot print messages to print platform features in a string
format. In the process, this patch moved relatively larger functions
to its own file from platform.h header file.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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As per the RISC-V specification, time value can be obtained from a time
CSR implemented in hardware or a MMIO based IP block. Qemu virt machine
already supports timer csr while CLINT provides the timer for other
platforms.
Implement a hart specific timer feature that can be detected at runtime.
As CSR based timer implementation are faster than MMIO address based, it
is always preferred over MMIO based one.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.
Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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There may be some features which are hart specific rather than a platform
specific feature. Add a framework to support that.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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There may be few common mathematics helper functions which can be used
anywhere in OpenSBI project.
Add a separate math helper function file to add these functions.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Unprivileged trap handler can be reused for any cases where the executing
code expects a trap.
Rename it to "expected" trap handler as it will be used in other cases in
future.
Signed-off-by: Atish Patra <[email protected]>
Tested-by: Jonathan Balkind <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The RISC-V ISA string does not follow alphabetical order. Instead,
we have a RISC-V specific ordering of extensions in the RISC-V ISA
string. This patch improves misa_string() implementation to return
a valid RISC-V ISA string.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The HFENCE VVMA instructions flushes TLB based on the VMID
present in HGATP CSR. To handle this, we get the current
VMID for SBI HFENCE VVMA call and we use this current VMID
to do remote TLB HFENCE VVMA on desired set of HARTs.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Now that we have generic platform which detects hart count from
DTB, we should print platform hart count at boot time.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We can achieve shutdown, cold reboot, and warm reboot using just
one sbi_platform callback so we combine system_reboot() and
system_shutdown() callbacks into one system_reset() callback.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The default (usually last) PMP region provides S-mode access to
complete memory range not covered by other PMP regions.
Currently, the default PMP region is described as platform specific
PMP region which is not appropriate because all platforms need it
and default PMP region should be part of generic library.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Ideally, the SBI implementation ID for OpenSBI should always be
0x1 (as mentioned in SBI v0.2 spec) but external firmware (such
as EDK2) which use OpenSBI as library might want to override the
SBI implementation ID with their custom implementation ID.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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Enable vector context in mstatus by updating the corresponding bits
in mstatus if vector extension is supported by the hart.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This patch removes scratch parameter from sbi_dprintf() function
because sbi_dprintf() can use sbi_scratch_thishart_ptr() to get
current HART scratch space.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch removes scratch parameter from most sbi_timer functions.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch removes scratch parameter and redundant functions from
sbi_system.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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This patch removes scratch parameter from most sbi_ipi functions.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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The sbi_ipi_send_many() should get current HART scratch pointer
on it's own using eventually hence removing scratch parameter from
sbi_tlb_request().
Signed-off-by: Anup Patel <[email protected]>
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The patch adds sbi_scratch_last_hartid() API which returns
last HART id having a scratch space. We can use this new API
to optimize places where we iterate over HART id from 0 to
SBI_HARTMASK_MAX_BITS.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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We should remove the "arch_" prefix from atomic xchg() and cmpxchg()
function names to have consistent naming of all atomic functions.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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