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The SiFive SMC0 controls the clock and power domain of the core complex
on the SiFive platform. The core complex enters the low power state
after the secondary cores enter the tile power gating and last core
execute the `CEASE` instruction with the corresponding SMC0
configurations. The devices that inside both tile power domain and core
complex power domain will be off, including caches and timer. Therefore
we need to flush the last level cache before entering the core complex
power gating and update the timer after waking up.
Reviewed-by: Cyan Yang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Nick Hu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>
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For driver subsystems that are not tightly integrated into the OpenSBI
init sequence, it is not important that the drivers are initialized in
any particular order. By putting all of these drivers in one array, they
can all be initialized with a single pass through the devicetree. This
saves about 10 ms of boot time on HiFive Unmatched.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add RPMI based system suspend driver.
To test this, execute the follwoing in Linux:
$ echo mem > /sys/power/state
To wake up, execute the following command on qemu monitor terminal:
(qemu) system_wakeup
Signed-off-by: Subrahmanya Lingappa <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
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The generic platform can have multiple system suspend drivers so add a
simple FDT based system suspend driver framework.
Signed-off-by: Anup Patel <[email protected]>
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