| Age | Commit message (Collapse) | Author |
|---|
|
The parser will fail if the timer is clint timer and has regname
property. As the regname is only meaningful for aclint, it is more
robust to only check regname for aclint timer.
Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT")
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.
If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.
Signed-off-by: Anup Patel <[email protected]>
|
|
Define an array sbi_hart_ext to map extension ID and name , and use it
for ISA parsing and printing out the supported extensions.
Signed-off-by: Yong-Xuan Wang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Currently, the fdt_parse_aclint_node() follows a fixed order to parse
ACLINT timer. This may cause the undesirable result when the ACLINT
device does not support mtime without adding an empty entry for it in
the DT.
To be robust, make fdt_parse_aclint_node() support "reg-names" property,
so it can parse the DT in an order independent way. For compatibility,
fdt_parse_aclint_node() only use "reg-names" when parsing ACLINT timer,
and will fallback to the old way if "reg-names" property is not found.
Link: https://lore.kernel.org/all/20231114-skedaddle-precinct-66c8897227bb@squawk/
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup patel <[email protected]>
|
|
The valid entry count is tracking by hw_event_count so there
is no need to check the whole table.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
To allow platform override pmu_init() filling the translation table
fdt_pmu_evt_select[] when PMU node doesn't provide such information,
we need to share the table and its entry counter with other .c file.
We also define the structures of PMU property in fdt_helper.h, so we
can initialize the mappings in arrays.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Add a Kconfig option to control PMU fixup, so the next
stage software can dump the PMU node including event
mapping information for debugging purposes.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This patch makes the following changes:
- As sbi_platform_pmu_init() returns a negative error code on
failure, let sbi_pmu_init() print out the error code with
sbi_dprintf().
- In order to distinguish the SBI_EFAIL error returned by
sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
generic_pmu_init() ignores such case.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
The old scheme doesn't allow sending hart0 self-IPI as the
corresponding bit on pending register is hardwired to 0, this
could lead to unhandle IPIs on SMP systems, esp. on single-core.
Furthermore, the limitation of old scheme is 8-core, instead of
reserving source hart information, we assign bit (x + 1) as the
enable and pending bit of hartx, this also expands the bootable
hart number.
The following diagram shows the enable bits of the new scheme
on 32-core Andes platform.
Pending regs: 0x1000 x---0---0---0---0------0---0
Pending hart ID: 0 1 2 3 ... 30 31
Interrupt ID: 0 1 2 3 4 ... 31 32
| | | | | | |
Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
| | | | | | |
0x2080 x---0---1---0---0-...--0---0---> hart1
| | | | | | |
0x2100 x---0---0---1---0-...--0---0---> hart2
| | | | | | |
0x2180 x---0---0---0---1-...--0---0---> hart3
. . . . . . .
. . . . . . .
. . . . . . .
0x2f00 x---0---0---0---0-...--1---0---> hart30
| | | | | | |
0x2f80 x---0---0---0---0-...--0---1---> hart31
<-------- word 0 -------><--- word 1 --->
To send IPI to hart0, for example, another hart (including hart0
itself) will set bit 1 of first word on the pending register.
We also fix indentation in andes_plicsw.h along with this patch.
Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support")
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Randolph <[email protected]>
Reported-by: Lad Prabhakar <[email protected]>
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
Reviewed-by: Lad Prabhakar <[email protected]>
Tested-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Currently, there are no barriers before or after the ipi_clear()
device callback which forces ipi_clear() device callback to always
use non-relaxed MMIO writes.
Instead of above, we use wmb() in after the ipi_clear() device
callback which pairs with the wmb() done before the ipi_send()
device callback. This also allows device ipi_clear() callback
to use relaxed MMIO writes.
Signed-off-by: Anup Patel <[email protected]>
Reported-by: Bo Gan <[email protected]>
|
|
Currently, we have a smp_wmb() between atomic_raw_set_bit() and
ipi_send() device callback whereas the MMIO writes done by the
device ipi_send() callback will also include a barrier.
We can avoid unnecessary/redundant barriers described above by
allowing relaxed MMIO writes in device ipi_send() callback. To
achieve this, we simply use wmb() instead of smp_wmb() before
calling device ipi_send().
Signed-off-by: Anup Patel <[email protected]>
Reported-by: Bo Gan <[email protected]>
|
|
Each APLIC CLRIE register allows disabling 32 interrupt sources at
a time by writing -1 so no need to write CLRIE register separately
for each interrupt source.
Fixes: 99792653de29 ("lib: utils/irqchip: Add APLIC initialization library")
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
|
|
For some debuggers that do not implement SYSWRITEC and SYSREADC
operations, we have to use SYSWRITE and SYSREAD.
Instead of implementing semihosting_putc() using SYSWRITE, let us
simply remove semihosting_putc() because console_putc/console_puts
are now interchangeable.
Signed-off-by: Chen Pei <[email protected]>
Signed-off-by: Xiang W <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
- Add Zkr as extension in sbi_hart_extensions enum
- Return "zkr" string for Zkr extension from sbi_hart_extension_id2string
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
string to avoid misuse.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang@outlook.com/
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang@outlook.com/
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs custom quirks.
Add a new quirk to identify custom ACLINT, and apply the general quirks
after applying CLINT specific quirks.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
In the past, we used fdt_reset_thead to help customers with prototype
verification. However, with the emergence of the Big-little SoC system,
it can no longer meet the demand. Therefore, we use zero_stage_boot
instead of fdt_reset_thead. It cleans up the opensbi code and ends the
disputation of reset_sample's dts.
This patch removes the fdt_reset_thead component and updates the related
doc.
Signed-off-by: Guo Ren <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
For some debuggers that do not implement SYSWRITEC and SYSREADC
operations, we can use SYSWRITE and SYSREAD instead like the
implementation of semihosting_getc().
Signed-off-by: Chen Pei <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
In starfive_gpio_direction_output() readl() is called twice to read the
gpio direction register. The result of the first read is discarded.
Remove the redundant read.
Fixes: 908be1b85c8f ("gpio/starfive: add gpio driver and support gpio reset")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The define is hard to read. The continue statement does not do what was
intended.
* Remove do {} while (false);
* Change the name to set_multi_letter_ext
- Other local macros are lower case too.
- Refer to the fact that this is only used for multi-letter extensions.
Addresses-Coverity-ID: 1568359 Unexpected control flow
Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA string in FDT")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
hart_exts == NULL can only occur if offset and node address lead to an
overflow resulting in exactly NULL. As we don't catch other values of
overflow it does not make sense to treat this one as special.
Addresses-Coverity-ID: 1568355 Logically dead code
Addresses-Coverity-ID: 1568358 Logically dead code
Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions() implementation")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.
With this update, both regions will become M-mode only read/write
regions in the root domain.
Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
p/x $pmpcfg0
$1 = {0x1f9b9b9d9b1e00,
pmp0cfg = {0x0},
L--AAXWR
pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1)
pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff
pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff
pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff
pmp7cfg = {0x0 }}
The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
p/x $pmpcfg0
$1 = {0x1f181818181b,
L--AAXWR
pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1)
pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff
pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff
pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff
pmp6cfg = {0x0 }}
Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The added memory region should start from the base address.
Otherwise, the range will be shifted by reg_offset and not
able to merge consecutive NAPOT regions in the root domain,
resulting in wasted PMP entries.
Fixes: e8bc1621 ("lib: utils/serial: Add shared regions for
serial drivers")
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
The syscon region used by OpenSBI should be marked as a shared
read-write region between M-mode and SU-mode.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Mayuresh Chitale <[email protected]>
|
|
The serial driver regions used by OpenSBI should be marked as a shared
read-write regions between M-mode and SU-mode as those are accessed
by earlycon and the corresponding tty serial drivers running in 'S' mode.
When the smepmp extension is enabled, PMP entries for these shared regions
will get programmed.
Signed-off-by: Mayuresh Chitale <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
Let us prefer hartindex over hartid in IPI framework which in-turn
forces IPI users to also prefer hartindex.
Signed-off-by: Anup Patel <[email protected]>
|
|
Currently, the sbi_hartmask is indexed by hartid which puts a
limit on hartid to be less than SBI_HARTMASK_MAX_BITS.
We extend the sbi_hartmask implementation to use hartindex and
support updating sbi_hartmask using hartid. This removes the
limit on hartid and existing code works largely unmodified.
Signed-off-by: Xiang W <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
|
|
Currently, the fdt_parse_isa_extensions() tries to parse the ISA
string once for each HART. This ISA string parsing can fail for
secondary HARTs if the FDT memory is already overwritten by the
supervisor OS.
To tackle this issue, we improve the fdt_parse_isa_extensions()
implementation to pre-parse ISA string for all HARTs during
cold boot.
Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA
string in FDT")
Signed-off-by: Anup Patel <[email protected]>
Tested-By: Mayuresh Chitale<[email protected]>
|
|
The functionality of SiFive Test reset driver is easily available
through Syscon reset driver so let us remove the SiFive Test driver.
Signed-off-by: Anup Patel <[email protected]>
|
|
Let us have common FDT based reset driver for syscon reboot and
poweroff. The device tree bindings for syscon reboot and poweroff
are already available in the Linux kernel sources.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
Let us add a simple FDT based system regmap driver which follows the
device tree bindings already defined in the Linux kernel.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
We add a simple FDT based regmap framework which is built on top of
generic regmap library. The phandle of FDT regmap DT node is treated
as unique regmap ID. The FDT based regmap drivers will be probed
on-demand from fdt_regmap_get_by_phandle() and fdt_regmap_get()
called by the regmap client drivers.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
We add generic regmap access library which is independent of
hardware description format (FDT or ACPI). The OpenSBI platform
support or regmap drivers can register regmap instances which
can be discovered by different regmap clients based on the
unique ID of regmap instances.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
The "driver" pointer in struct i2c_adapter is not used anywhere
so let us remove it.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
License identifiers should be machine readable.
According to the SPDX v2.3.0 specification annex E parentheses are not
used in the SPDX identifier field when specifying multiple licenses [1].
[1] https://spdx.github.io/spdx-spec/v2.3/using-SPDX-short-identifiers-in-source-files/
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
- Add function to parse ISA string in FDT.
- Set Smepmp feature bit in extensions if "smepmp" string is found in ISA string.
Signed-off-by: Himanshu Chauhan <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
Currently, we see following compile error in the designeware GPIO driver
for RV32 systems:
lib/utils/gpio/fdt_gpio_designware.c:115:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
115 | chip->dr = (void *)addr + (bank * 0xc);
| ^
lib/utils/gpio/fdt_gpio_designware.c:116:21: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
116 | chip->ext = (void *)addr + (bank * 4) + 0x50;
We fix the above error using an explicit type-cast to 'unsigned long'.
Fixes: 7828eebaaa77 ("gpio/desginware: add Synopsys DesignWare APB GPIO support")
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
The cold_init() functions of ACLINT drivers should skip the HART
if sbi_hartid_to_scratch() returns NULL because we might be dealing
with a HART that is disabled in the device tree.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
Add a driver for the Synopsys DesignWare APB GPIO IP block found in many
SoCs.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
|
|
This reverts commit 6966ad0abe70 ("platform/lib: Allow the OS to map the
regions that are protected by PMP").
It was thought at the time of this commit that allowing the kernel to map
PMP protected regions was safe but it is actually not: for example, the
hibernation process will try to access any linear mapping page and then
will fault on such mapped PMP regions [1]. Another issue is that the
device tree specification [2] states that a !no-map region must be
declared as EfiBootServicesData/Code in the EFI memory map which would make
the PMP protected regions reclaimable by the kernel. And to circumvent
this, RISC-V edk2 diverges from the DT specification to declare those
regions as EfiReserved.
The no-map attribute was removed to allow the kernel to use hugepages
larger than 2MB to map the linear mapping to improve the performance but
actually a recent talk from Mike Rapoport [3] stated that the
performance benefit was marginal.
For all those reasons, let's mark all the PMP protected regions as "no-map".
[1] https://lore.kernel.org/linux-riscv/CAAYs2=gQvkhTeioMmqRDVGjdtNF_vhB+vm_1dHJxPNi75YDQ_Q@mail.gmail.com/
[2] "3.5.4 /reserved-memory and UEFI" https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4-rc1/devicetree-specification-v0.4-rc1.pdf
[3] https://lwn.net/Articles/931406/
Signed-off-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Xiang W <[email protected]>
|
|
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART IMSIC pointer and IMSIC file number.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
The imsic_map_hartid_to_data() already checks hartid before using
so we don't need to check in imsic_update_hartid_table().
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART PLIC pointer and PLIC context numbers.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART MTIMER pointer.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART MSWI pointer.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Let's use heap allocation in FDT domain parsing instead of using
a fixed size global array.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Let's use heap allocation in ACLINT MTIMER driver instead of using
a fixed size global array.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Let's use heap allocation in PLIC, APLIC, and IMSIC irqchip drivers
instead of using a fixed size global array.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
|
Let's use heap allocation in ACLINT MSWI driver instead of using
a fixed size global array.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
|
