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pmic_ops() is only called if a compatible device is found in device
tree. It is redundant for this function to check the compability again.
Remove this check.
Signed-off-by: Nam Cao <[email protected]>
Tested-by: Minda Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The current code gets the I2C offset address using the device tree node
name: it get the I2C device index from the 4th character in the node
name (for example, "i2c5" -> i2c device 5). However, the device tree
node's name in U-Boot is actually just "i2c" without the number, so the
current code cannot be used with the device tree from U-Boot.
Get the I2C offset address from the "clocks" property instead.
Signed-off-by: Nam Cao <[email protected]>
Reviewed-by: Minda Chen <[email protected]>
Tested-by: Minda Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Starfive names the system clock device tree node "starfive,jh7110-clkgen"
in all their git repositories. However, a different name is used in
upstream U-Boot (and also Linux): "starfive,jh7110-syscrg". Since
OpenSBI gets the device tree from U-Boot, this inconsistency leads the
problem that OpenSBI doesn't know the system clock device exists.
Correct this name to keep the consistency.
Signed-off-by: Nam Cao <[email protected]>
Acked-by: Minda Chen <[email protected]>
Tested-by: Minda Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This patch update generic_domains_init() so that "system-suspend-test"
is parsed from "/chosen/opensbi-config" DT node.
Signed-off-by: Cheng Yang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Added support for the generic platform to specify the set of coldboot
hart in DT. If not specified in DT, all harts are allowed to coldboot
as before.
The functions related to sbi_hartmask are not available before coldboot,
so I used bitmap, and added a new bitmap_test() function to test whether
a certain bit of the bitmap is set.
Signed-off-by: Cheng Yang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Some of the upcoming SBI extensions (such as SSE) will directly
update register state so improve the prototype of ecall handler
to accommodate this. Further, this flexibility allows us to
push the trap redirection from sbi_ecall_handler() to the
sbi_ecall_legacy_handler().
Signed-off-by: Anup Patel <[email protected]>
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Let's use SBI_TLB_INFO_SIZE instead of hard-coded 0x40 in
fw_platform_calculate_heap_size() to fine tune the heap size
required for per-hart TLB fifos.
Signed-off-by: Anup Patel <[email protected]>
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Previous patch introduced a change that using hart count as the default
number of tlb entries in the fifo. This makes the default tlb fifo size
grow in square with the number of harts. So the default heap size is
not enough to allocate tlb fifo when the hart count is big.
Fixes: 52fd64b ("platform: Uses hart count as the default size of tlb info")
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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We will need is_andes(45) in the following patch,
so factor out the code that parses marchid to make
it reusable for checking any Andes CPU variants.
Also improves the comment in ae350_hart_start().
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Enable Andes PMU extension support for RZ/Five.
We also staticize renesas_rzfive_early_init() as
it is not used outside of this unit.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Tested-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Enable Andes PMU extension support for AE350 platforms.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Tested-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Before the ratification of Sscofpmf, the Andes PMU extension
was designed to support the sampling and filtering with hardware
performance counters (zihpm), it works with the current SBI PMU
extension and Linux SBI PMU driver.
We implement 1) the PMU device callbacks that update the
corresponding bits on custom CSRs, 2) extentions_init() to detect
the hardware support of Andes PMU and initialize the per-hart
PMU related CSR, and 3) pmu_init() to register PMU device and
populate event mappings.
Also define a andes_pmu_setup() function which is in preparation
for adding default PMU mappings in andes_hpm.h
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add pmu_init() platform override, which will be used to register
PMU device and populate event mappings.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add CSR definitions for Andes PMU extension.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Tested-by: Lad Prabhakar <[email protected]>
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This patch makes the following changes:
- As sbi_platform_pmu_init() returns a negative error code on
failure, let sbi_pmu_init() print out the error code with
sbi_dprintf().
- In order to distinguish the SBI_EFAIL error returned by
sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
generic_pmu_init() ignores such case.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
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In the future there may be a lot of ISA extensions, a 'long' may not
be able to accommodate, changed to an array for the future.
Addresses-Coverity-ID: 1568357 Out-of-bounds access
Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions()
implementation")
Signed-off-by: Xiang W <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add Sophgo sg2042 soc support
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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In the past, we used fdt_reset_thead to help customers with prototype
verification. However, with the emergence of the Big-little SoC system,
it can no longer meet the demand. Therefore, we use zero_stage_boot
instead of fdt_reset_thead. It cleans up the opensbi code and ends the
disputation of reset_sample's dts.
This patch removes the fdt_reset_thead component and updates the related
doc.
Signed-off-by: Guo Ren <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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For platform with high number of harts, it is better to auto detect a
suitable number of entries in tlb fifo. Since allocating tlb entry for
all online harts can reduce the wait time significantly, using the
number of the online harts can make most platforms happy. This auto
detection can avoid most duplicate code for setting tlb fifo size.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Guo Ren <[email protected]>
Reviewed-by: Xiang W <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Flushing the tlb entries can solve the thead tlb problem, but flushing
it by address will miss something and lead to a exception in some rare
cases, and this is more common for sg2042.
To solve this problem, flush the tlb entries by asid in the custom trap
handler to ensure it is refreshed.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Since all the SoC with thead c9xx cores need this initialization at now,
initialize the c9xx pmu in the thead generic platform by default.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Separate the implement of T-HEAD c9xx errata to allow any platform
with bug related to c9xx cores can use it.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The CSR encoding for t-head c9xx cores is shared across all the
platforms with these cores. So move header thead_c9xx.h to the
thead subdir.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The TLB entries remain functional all the time once added in T-HEAD th1520
and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there
are some stale TLB entries that contains the address of SBI, it will cause
unexpected memory access and issue a illegal instruction error. To avoid
this, a TLB flush is needed to drop these TLB entries before any memory
access in the trap handler.
To handle this workaroud, add a custom trap handler with executing TLB flush
first in the T-HEAD platform to fix affected socs.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Let us prefer hartindex over hartid in IPI framework which in-turn
forces IPI users to also prefer hartindex.
Signed-off-by: Anup Patel <[email protected]>
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For some platforms with a particularly high number of harts, if the
tlb fifo is too small, it case harts to wait. Platforms should be
allowed to specify the size of the tlb fifo.
Signed-off-by: Xiang W <[email protected]>
Signed-off-by: Xing Xiaoguang <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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T-HEAD c9xx pmu needs to clear OV bits of MCOUNTEROF in any condition
to avoid unnecessary OF interrupts.
In addition, the S-mode SCOUNTEROF only have OF bit set when the related
bits of MCOUNTERWEN is set, so also configure MCOUNTERWEN to allow kernel
to access valid SCOUNTEROF.
Signed-off-by: Haijiao Liu <[email protected]>
Co-authored-by: Inochi Amaoto <[email protected]>
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Tested-by: Samuel Holland <[email protected]>
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Only the CSR mhpmevent 3-9,13-17 of D1 have valid function, so change
the mhpm_mask to a valid value to avoid invalid usage.
Due to the openc906 pmu code
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The functionality of SiFive Test reset driver is easily available
through Syscon reset driver so let us remove the SiFive Test driver.
Signed-off-by: Anup Patel <[email protected]>
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Let us have common FDT based reset driver for syscon reboot and
poweroff. The device tree bindings for syscon reboot and poweroff
are already available in the Linux kernel sources.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
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Let us add a simple FDT based system regmap driver which follows the
device tree bindings already defined in the Linux kernel.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
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We add a simple FDT based regmap framework which is built on top of
generic regmap library. The phandle of FDT regmap DT node is treated
as unique regmap ID. The FDT based regmap drivers will be probed
on-demand from fdt_regmap_get_by_phandle() and fdt_regmap_get()
called by the regmap client drivers.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
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We add generic regmap access library which is independent of
hardware description format (FDT or ACPI). The OpenSBI platform
support or regmap drivers can register regmap instances which
can be discovered by different regmap clients based on the
unique ID of regmap instances.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Xiang W <[email protected]>
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- Add function to parse ISA string in FDT.
- Set Smepmp feature bit in extensions if "smepmp" string is found in ISA string.
Signed-off-by: Himanshu Chauhan <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add a driver for the Synopsys DesignWare APB GPIO IP block found in many
SoCs.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The fdt_reset_thead driver needs to modify the __reset_thead_csr_stub
text region for the secondary harts booting. After that, the
sbi_hart_pmp_configure may lock down the text region with M_READABLE &
M_EXECUTABLE attributes in the future. Currently, the M_READABLE &
M_EXECUtABLE have no effect on m-mode, the L-bit in pmpcfg csr is
useless for the current opensbi scenario. See:
Priv-isa-spec 3.7.1.2. Locking and Privilege Mode
When the L bit is clear, any M-mode access matching the PMP entry will
succeed; the R/W/X permissions apply only to S and U modes.
That's why current fdt_reset_thead could still work well after commit:
230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW
regions"). So this patch fixes up a fake bug for the M-mode permission
setting of the future.
Fixes: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions")
Link: http://lists.infradead.org/pipermail/opensbi/2023-June/005176.html
Reported-by: Jessica Clarke <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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This reverts commit 6966ad0abe70 ("platform/lib: Allow the OS to map the
regions that are protected by PMP").
It was thought at the time of this commit that allowing the kernel to map
PMP protected regions was safe but it is actually not: for example, the
hibernation process will try to access any linear mapping page and then
will fault on such mapped PMP regions [1]. Another issue is that the
device tree specification [2] states that a !no-map region must be
declared as EfiBootServicesData/Code in the EFI memory map which would make
the PMP protected regions reclaimable by the kernel. And to circumvent
this, RISC-V edk2 diverges from the DT specification to declare those
regions as EfiReserved.
The no-map attribute was removed to allow the kernel to use hugepages
larger than 2MB to map the linear mapping to improve the performance but
actually a recent talk from Mike Rapoport [3] stated that the
performance benefit was marginal.
For all those reasons, let's mark all the PMP protected regions as "no-map".
[1] https://lore.kernel.org/linux-riscv/CAAYs2=gQvkhTeioMmqRDVGjdtNF_vhB+vm_1dHJxPNi75YDQ_Q@mail.gmail.com/
[2] "3.5.4 /reserved-memory and UEFI" https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4-rc1/devicetree-specification-v0.4-rc1.pdf
[3] https://lwn.net/Articles/931406/
Signed-off-by: Alexandre Ghiti <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Xiang W <[email protected]>
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We extend struct sbi_platform and struct sbi_scratch to allow platforms
specify the heap size to the OpenSBI firmwares. The OpenSBI firmwares
will use this information to determine the location of heap and provide
heap base address in per-HART scratch space.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
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I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.
IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC (which is based on Andes AX45MP core) due to this reason IP blocks
using DMA will fail.
As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.
SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be
applied to handle cache management.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
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add reboot and poweroff support. The whole reboot and shutdown
pm op includes shutdown jh7110 pmu device power domain
and access on board pmic register through I2C.
Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add gpio driver and gpio reset function in Starfive
JH7110 SOC platform.
Signed-off-by: minda.chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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When the system-suspend-test property is present in the domain config
node as shown below, implement system suspend with a simple 5 second
delay followed by a WFI. This allows testing system suspend when the
low-level firmware doesn't support it.
/ {
chosen {
opensbi-domains {
compatible = "opensbi,domain,config";
system-suspend-test;
};
Signed-off-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory
ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA
and populate this region as PMA reserve DT node with shared DMA pool and
no-map flags set so that Linux drivers requesting any DMA'able memory go
through this region.
PMA node passed to the above stack:
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pma_resv0@58000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x58000000 0x0 0x08000000>;
no-map;
linux,dma-default;
};
};
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.
IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC due to this reason IP blocks using DMA will fail.
The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
Below are the memory attributes supported:
* Device, Non-bufferable
* Device, bufferable
* Memory, Non-cacheable, Non-bufferable
* Memory, Non-cacheable, Bufferable
* Memory, Write-back, No-allocate
* Memory, Write-back, Read-allocate
* Memory, Write-back, Write-allocate
* Memory, Write-back, Read and Write-allocate
More info about PMA (section 10.3):
Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.
Example PMA region passed as a DT node from OpenSBI:
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pma_resv0@58000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x58000000 0x0 0x08000000>;
no-map;
linux,dma-default;
};
};
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The extid parameter of vendor_ext_provider() is redundant so let us
remove it.
Signed-off-by: Anup Patel <[email protected]>
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As-per the SBI specification, the lower 24bits of the SBI vendor
extension id is same as lower 24bits of the mvendorid CSR.
We update the SBI vendor extension id checking based on above.
Signed-off-by: Anup Patel <[email protected]>
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The code calls various macros from riscv_asm.h which is not directly
included. Fix such dependency.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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The code calls various macros from riscv_asm.h and sbi_scratch.h
which are not directly included. Fix such dependency.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
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Add D1's nonretentive suspend state to the devicetree so S-mode software
knows about it and can use it.
Latency and power measurements were taken on an Allwinner Nezha board:
- Entry latency was measured from the beginning of sbi_ecall_handler()
to before the call to wfi() in sun20i_d1_hart_suspend().
- Exit latency was measured from the beginning of sbi_init() to before
the call to sbi_hart_switch_mode() in init_warmboot().
- There was a 17.5 mW benefit from non-retentive suspend compared to
WFI, with a 170 mW cost during the 107 us entry/exit period. This
provides a break-even point around 1040 us. Residency includes entry
latency, so round this up to 1100 us.
- The hardware power sequence latency (after the WFI) is assumed to be
negligible, so set the wakeup latency to the exit latency.
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
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