From 13877c3a6752138018f99214273dc3d7376cf5eb Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Sat, 30 Mar 2019 17:43:23 +0530 Subject: include: Rename sbi_unpriv.h to riscv_unpriv.h The sbi_unpriv.h has quite a few load_xyz() and store_xyz() helper routines based on RISC-V inline assembly for unpriviledged accesses from M-mode. These helper routines are similar to helper routines present in riscv_locks.h, riscv_io.h, and riscv_atomic.h so let's rename sbi_unpriv.h to riscv_unpriv.h. Signed-off-by: Anup Patel --- include/sbi/riscv_unpriv.h | 117 +++++++++++++++++++++++++++++++++++++++++++++ include/sbi/sbi_unpriv.h | 117 --------------------------------------------- lib/sbi_illegal_insn.c | 2 +- lib/sbi_ipi.c | 2 +- lib/sbi_misaligned_ldst.c | 2 +- 5 files changed, 120 insertions(+), 120 deletions(-) create mode 100644 include/sbi/riscv_unpriv.h delete mode 100644 include/sbi/sbi_unpriv.h diff --git a/include/sbi/riscv_unpriv.h b/include/sbi/riscv_unpriv.h new file mode 100644 index 00000000..c1094176 --- /dev/null +++ b/include/sbi/riscv_unpriv.h @@ -0,0 +1,117 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_UNPRIV_H__ +#define __RISCV_UNPRIV_H__ + +#include +#include +#include + +#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ +static inline type load_##type(const type *addr) \ +{ \ + register ulong __mstatus asm ("a2"); \ + type val; \ + asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ + #insn " %1, %2\n" \ + "csrw "STR(CSR_MSTATUS)", %0" \ + : "+&r" (__mstatus), "=&r" (val) \ + : "m" (*addr), "r" (MSTATUS_MPRV)); \ + return val; \ +} + +#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ +static inline void store_##type(type *addr, type val) \ +{ \ + register ulong __mstatus asm ("a3"); \ + asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ + #insn " %1, %2\n" \ + "csrw "STR(CSR_MSTATUS)", %0" \ + : "+&r" (__mstatus) \ + : "r" (val), "m" (*addr), "r" (MSTATUS_MPRV)); \ +} + +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw) +DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb) +DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh) +DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw) +#if __riscv_xlen == 64 +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld) +DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) +#else +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) +DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) + +static inline u64 load_u64(const u64 *addr) +{ + return load_u32((u32 *)addr) + + ((u64)load_u32((u32 *)addr + 1) << 32); +} + +static inline void store_u64(u64 *addr, u64 val) +{ + store_u32((u32 *)addr, val); + store_u32((u32 *)addr + 1, val >> 32); +} +#endif + +static inline ulong get_insn(ulong mepc, ulong *mstatus) +{ + register ulong __mepc asm ("a2") = mepc; + register ulong __mstatus asm ("a3"); + ulong val; +#ifndef __riscv_compressed + asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" +#if __riscv_xlen == 64 + STR(LWU) " %[insn], (%[addr])\n" +#else + STR(LW) " %[insn], (%[addr])\n" +#endif + "csrw "STR(CSR_MSTATUS)", %[mstatus]" + : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val) + : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc)); +#else + ulong rvc_mask = 3, tmp; + asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" + "and %[tmp], %[addr], 2\n" + "bnez %[tmp], 1f\n" +#if __riscv_xlen == 64 + STR(LWU) " %[insn], (%[addr])\n" +#else + STR(LW) " %[insn], (%[addr])\n" +#endif + "and %[tmp], %[insn], %[rvc_mask]\n" + "beq %[tmp], %[rvc_mask], 2f\n" + "sll %[insn], %[insn], %[xlen_minus_16]\n" + "srl %[insn], %[insn], %[xlen_minus_16]\n" + "j 2f\n" + "1:\n" + "lhu %[insn], (%[addr])\n" + "and %[tmp], %[insn], %[rvc_mask]\n" + "bne %[tmp], %[rvc_mask], 2f\n" + "lhu %[tmp], 2(%[addr])\n" + "sll %[tmp], %[tmp], 16\n" + "add %[insn], %[insn], %[tmp]\n" + "2: csrw "STR(CSR_MSTATUS)", %[mstatus]" + : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val), [tmp] "=&r" (tmp) + : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc), + [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (__riscv_xlen - 16)); +#endif + *mstatus = __mstatus; + return val; +} + +#endif diff --git a/include/sbi/sbi_unpriv.h b/include/sbi/sbi_unpriv.h deleted file mode 100644 index 2d9dbb97..00000000 --- a/include/sbi/sbi_unpriv.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel - */ - -#ifndef __SBI_UNPRIV_H__ -#define __SBI_UNPRIV_H__ - -#include -#include -#include - -#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ -static inline type load_##type(const type *addr) \ -{ \ - register ulong __mstatus asm ("a2"); \ - type val; \ - asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ - #insn " %1, %2\n" \ - "csrw "STR(CSR_MSTATUS)", %0" \ - : "+&r" (__mstatus), "=&r" (val) \ - : "m" (*addr), "r" (MSTATUS_MPRV)); \ - return val; \ -} - -#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ -static inline void store_##type(type *addr, type val) \ -{ \ - register ulong __mstatus asm ("a3"); \ - asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n" \ - #insn " %1, %2\n" \ - "csrw "STR(CSR_MSTATUS)", %0" \ - : "+&r" (__mstatus) \ - : "r" (val), "m" (*addr), "r" (MSTATUS_MPRV)); \ -} - -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw) -#if __riscv_xlen == 64 -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) -#else -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) - -static inline u64 load_u64(const u64 *addr) -{ - return load_u32((u32 *)addr) - + ((u64)load_u32((u32 *)addr + 1) << 32); -} - -static inline void store_u64(u64 *addr, u64 val) -{ - store_u32((u32 *)addr, val); - store_u32((u32 *)addr + 1, val >> 32); -} -#endif - -static inline ulong get_insn(ulong mepc, ulong *mstatus) -{ - register ulong __mepc asm ("a2") = mepc; - register ulong __mstatus asm ("a3"); - ulong val; -#ifndef __riscv_compressed - asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" -#if __riscv_xlen == 64 - STR(LWU) " %[insn], (%[addr])\n" -#else - STR(LW) " %[insn], (%[addr])\n" -#endif - "csrw "STR(CSR_MSTATUS)", %[mstatus]" - : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val) - : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc)); -#else - ulong rvc_mask = 3, tmp; - asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n" - "and %[tmp], %[addr], 2\n" - "bnez %[tmp], 1f\n" -#if __riscv_xlen == 64 - STR(LWU) " %[insn], (%[addr])\n" -#else - STR(LW) " %[insn], (%[addr])\n" -#endif - "and %[tmp], %[insn], %[rvc_mask]\n" - "beq %[tmp], %[rvc_mask], 2f\n" - "sll %[insn], %[insn], %[xlen_minus_16]\n" - "srl %[insn], %[insn], %[xlen_minus_16]\n" - "j 2f\n" - "1:\n" - "lhu %[insn], (%[addr])\n" - "and %[tmp], %[insn], %[rvc_mask]\n" - "bne %[tmp], %[rvc_mask], 2f\n" - "lhu %[tmp], 2(%[addr])\n" - "sll %[tmp], %[tmp], 16\n" - "add %[insn], %[insn], %[tmp]\n" - "2: csrw "STR(CSR_MSTATUS)", %[mstatus]" - : [mstatus] "+&r" (__mstatus), [insn] "=&r" (val), [tmp] "=&r" (tmp) - : [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc), - [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (__riscv_xlen - 16)); -#endif - *mstatus = __mstatus; - return val; -} - -#endif diff --git a/lib/sbi_illegal_insn.c b/lib/sbi_illegal_insn.c index 58567f46..820f96c5 100644 --- a/lib/sbi_illegal_insn.c +++ b/lib/sbi_illegal_insn.c @@ -9,12 +9,12 @@ #include #include +#include #include #include #include #include #include -#include typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause, diff --git a/lib/sbi_ipi.c b/lib/sbi_ipi.c index 609de0df..471b5939 100644 --- a/lib/sbi_ipi.c +++ b/lib/sbi_ipi.c @@ -11,13 +11,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include static int sbi_ipi_send(struct sbi_scratch *scratch, u32 hartid, u32 event, void *data) diff --git a/lib/sbi_misaligned_ldst.c b/lib/sbi_misaligned_ldst.c index f1df3f02..3fe67ea6 100644 --- a/lib/sbi_misaligned_ldst.c +++ b/lib/sbi_misaligned_ldst.c @@ -9,11 +9,11 @@ #include #include +#include #include #include #include #include -#include union reg_data { u8 data_bytes[8]; -- cgit v1.3.1