From 59688948421deea18993836152af66765bdc76f6 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 23 Mar 2020 12:48:54 -0700 Subject: platform: Move ariane standalone fpga project to its own project Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- docs/platform/ariane-fpga.md | 38 -------- docs/platform/fpga-ariane.md | 38 ++++++++ docs/platform/platform.md | 2 +- platform/ariane-fpga/config.mk | 36 ------- platform/ariane-fpga/objects.mk | 8 -- platform/ariane-fpga/platform.c | 206 --------------------------------------- platform/fpga/ariane/config.mk | 36 +++++++ platform/fpga/ariane/objects.mk | 8 ++ platform/fpga/ariane/platform.c | 206 +++++++++++++++++++++++++++++++++++++++ scripts/create-binary-archive.sh | 2 +- 10 files changed, 290 insertions(+), 290 deletions(-) delete mode 100644 docs/platform/ariane-fpga.md create mode 100644 docs/platform/fpga-ariane.md delete mode 100644 platform/ariane-fpga/config.mk delete mode 100644 platform/ariane-fpga/objects.mk delete mode 100644 platform/ariane-fpga/platform.c create mode 100644 platform/fpga/ariane/config.mk create mode 100644 platform/fpga/ariane/objects.mk create mode 100644 platform/fpga/ariane/platform.c diff --git a/docs/platform/ariane-fpga.md b/docs/platform/ariane-fpga.md deleted file mode 100644 index 98cbc87a..00000000 --- a/docs/platform/ariane-fpga.md +++ /dev/null @@ -1,38 +0,0 @@ -Ariane FPGA SoC Platform -======================== -Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit -RISC-V instruction set. The Ariane FPGA development platform is based on FPGA -SoC (which currently supports only Genesys 2 board) and is capable of running -Linux. - -The FPGA SoC currently contains the following peripherals: -- DDR3 memory controller -- SPI controller to conncet to an SDCard -- Ethernet controller -- JTAG port (see debugging section below) -- Bootrom containing zero stage bootloader and device tree. - -To build platform specific library and firmwares, provide the -*PLATFORM=ariane-fpga* parameter to the top level `make` command. - -Platform Options ----------------- - -The *Ariane FPGA* platform does not have any platform-specific options. - -Building Ariane FPGA Platform ------------------------------ - -**Linux Kernel Payload** - -``` -make PLATFORM=ariane-fpga FW_PAYLOAD_PATH=/arch/riscv/boot/Image -``` - -Booting Ariane FPGA Platform ----------------------------- - -**Linux Kernel Payload** - -As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will -directly boot into Linux directly after powered on. diff --git a/docs/platform/fpga-ariane.md b/docs/platform/fpga-ariane.md new file mode 100644 index 00000000..f95001fb --- /dev/null +++ b/docs/platform/fpga-ariane.md @@ -0,0 +1,38 @@ +Ariane FPGA SoC Platform +======================== +Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit +RISC-V instruction set. The Ariane FPGA development platform is based on FPGA +SoC (which currently supports only Genesys 2 board) and is capable of running +Linux. + +The FPGA SoC currently contains the following peripherals: +- DDR3 memory controller +- SPI controller to conncet to an SDCard +- Ethernet controller +- JTAG port (see debugging section below) +- Bootrom containing zero stage bootloader and device tree. + +To build platform specific library and firmwares, provide the +*PLATFORM=fpga/ariane* parameter to the top level `make` command. + +Platform Options +---------------- + +The *Ariane FPGA* platform does not have any platform-specific options. + +Building Ariane FPGA Platform +----------------------------- + +**Linux Kernel Payload** + +``` +make PLATFORM=fpga/ariane FW_PAYLOAD_PATH=/arch/riscv/boot/Image +``` + +Booting Ariane FPGA Platform +---------------------------- + +**Linux Kernel Payload** + +As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will +directly boot into Linux directly after powered on. diff --git a/docs/platform/platform.md b/docs/platform/platform.md index 2efa8b36..d34ce7a2 100644 --- a/docs/platform/platform.md +++ b/docs/platform/platform.md @@ -33,7 +33,7 @@ facilitate the implementation. [qemu_virt.md]: qemu_virt.md [sifive_fu540.md]: sifive_fu540.md -[ariane-fpga.md]: ariane-fpga.md +[fpga-ariane.md]: fpga-ariane.md [andes_ae350.md]: andes-ae350.md [thead-c910.md]: thead-c910.md [spike.md]: spike.md diff --git a/platform/ariane-fpga/config.mk b/platform/ariane-fpga/config.mk deleted file mode 100644 index 3556461a..00000000 --- a/platform/ariane-fpga/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# SPDX-License-Identifier: BSD-2-Clause -# -# Copyright (C) 2019 FORTH-ICS/CARV -# Panagiotis Peristerakis -# - -#for more infos, check out /platform/template/config.mk - -PLATFORM_RISCV_XLEN = 64 - -# Blobs to build -FW_TEXT_START=0x80000000 -FW_JUMP=n - -ifeq ($(PLATFORM_RISCV_XLEN), 32) - # This needs to be 4MB aligned for 32-bit support - FW_JUMP_ADDR=0x80400000 - else - # This needs to be 2MB aligned for 64-bit support - FW_JUMP_ADDR=0x80200000 - endif -FW_JUMP_FDT_ADDR=0x82200000 - -# Firmware with payload configuration. -FW_PAYLOAD=y - -ifeq ($(PLATFORM_RISCV_XLEN), 32) -# This needs to be 4MB aligned for 32-bit support - FW_PAYLOAD_OFFSET=0x400000 -else -# This needs to be 2MB aligned for 64-bit support - FW_PAYLOAD_OFFSET=0x200000 -endif -FW_PAYLOAD_FDT_ADDR=0x82200000 -FW_PAYLOAD_ALIGN=0x1000 diff --git a/platform/ariane-fpga/objects.mk b/platform/ariane-fpga/objects.mk deleted file mode 100644 index 814e6da6..00000000 --- a/platform/ariane-fpga/objects.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPDX-License-Identifier: BSD-2-Clause -# -# Copyright (C) 2019 FORTH-ICS/CARV -# Panagiotis Peristerakis -# - -platform-objs-y += platform.o diff --git a/platform/ariane-fpga/platform.c b/platform/ariane-fpga/platform.c deleted file mode 100644 index bba04d63..00000000 --- a/platform/ariane-fpga/platform.c +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ -/* - * Copyright (C) 2019 FORTH-ICS/CARV - * Panagiotis Peristerakis - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ARIANE_UART_ADDR 0x10000000 -#define ARIANE_UART_FREQ 50000000 -#define ARIANE_UART_BAUDRATE 115200 -#define ARIANE_UART_REG_SHIFT 2 -#define ARIANE_UART_REG_WIDTH 4 -#define ARIANE_PLIC_ADDR 0xc000000 -#define ARIANE_PLIC_NUM_SOURCES 3 -#define ARIANE_HART_COUNT 1 -#define ARIANE_CLINT_ADDR 0x2000000 -#define PLIC_ENABLE_BASE 0x2000 -#define PLIC_ENABLE_STRIDE 0x80 -#define PLIC_CONTEXT_BASE 0x200000 -#define PLIC_CONTEXT_STRIDE 0x1000 - -#define SBI_ARIANE_FEATURES \ - (SBI_PLATFORM_HAS_TIMER_VALUE | \ - SBI_PLATFORM_HAS_SCOUNTEREN | \ - SBI_PLATFORM_HAS_MCOUNTEREN | \ - SBI_PLATFORM_HAS_MFAULTS_DELEGATION) - - -/* - * Ariane platform early initialization. - */ -static int ariane_early_init(bool cold_boot) -{ - /* For now nothing to do. */ - return 0; -} - -/* - * Ariane platform final initialization. - */ -static int ariane_final_init(bool cold_boot) -{ - void *fdt; - - if (!cold_boot) - return 0; - - fdt = sbi_scratch_thishart_arg1_ptr(); - fdt_fixups(fdt); - - return 0; -} - -/* - * Initialize the ariane console. - */ -static int ariane_console_init(void) -{ - return uart8250_init(ARIANE_UART_ADDR, - ARIANE_UART_FREQ, - ARIANE_UART_BAUDRATE, - ARIANE_UART_REG_SHIFT, - ARIANE_UART_REG_WIDTH); -} - -static int plic_ariane_warm_irqchip_init(u32 target_hart, - int m_cntx_id, int s_cntx_id) -{ - size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1; - - if (ARIANE_HART_COUNT <= target_hart) - return -1; - /* By default, enable all IRQs for M-mode of target HART */ - if (m_cntx_id > -1) { - for (i = 0; i < ie_words; i++) - plic_set_ie(m_cntx_id, i, 1); - } - /* Enable all IRQs for S-mode of target HART */ - if (s_cntx_id > -1) { - for (i = 0; i < ie_words; i++) - plic_set_ie(s_cntx_id, i, 1); - } - /* By default, enable M-mode threshold */ - if (m_cntx_id > -1) - plic_set_thresh(m_cntx_id, 1); - /* By default, disable S-mode threshold */ - if (s_cntx_id > -1) - plic_set_thresh(s_cntx_id, 0); - - return 0; -} - -/* - * Initialize the ariane interrupt controller for current HART. - */ -static int ariane_irqchip_init(bool cold_boot) -{ - u32 hartid = current_hartid(); - int ret; - - if (cold_boot) { - ret = plic_cold_irqchip_init(ARIANE_PLIC_ADDR, - ARIANE_PLIC_NUM_SOURCES, - ARIANE_HART_COUNT); - if (ret) - return ret; - } - return plic_ariane_warm_irqchip_init(hartid, - 2 * hartid, 2 * hartid + 1); -} - -/* - * Initialize IPI for current HART. - */ -static int ariane_ipi_init(bool cold_boot) -{ - int ret; - - if (cold_boot) { - ret = clint_cold_ipi_init(ARIANE_CLINT_ADDR, - ARIANE_HART_COUNT); - if (ret) - return ret; - } - - return clint_warm_ipi_init(); -} - -/* - * Initialize ariane timer for current HART. - */ -static int ariane_timer_init(bool cold_boot) -{ - int ret; - - if (cold_boot) { - ret = clint_cold_timer_init(ARIANE_CLINT_ADDR, - ARIANE_HART_COUNT, TRUE); - if (ret) - return ret; - } - - return clint_warm_timer_init(); -} - -/* - * Reboot the ariane. - */ -static int ariane_system_reboot(u32 type) -{ - /* For now nothing to do. */ - sbi_printf("System reboot\n"); - return 0; -} - -/* - * Shutdown or poweroff the ariane. - */ -static int ariane_system_shutdown(u32 type) -{ - /* For now nothing to do. */ - sbi_printf("System shutdown\n"); - return 0; -} - -/* - * Platform descriptor. - */ -const struct sbi_platform_operations platform_ops = { - .early_init = ariane_early_init, - .final_init = ariane_final_init, - .console_init = ariane_console_init, - .console_putc = uart8250_putc, - .console_getc = uart8250_getc, - .irqchip_init = ariane_irqchip_init, - .ipi_init = ariane_ipi_init, - .ipi_send = clint_ipi_send, - .ipi_clear = clint_ipi_clear, - .timer_init = ariane_timer_init, - .timer_value = clint_timer_value, - .timer_event_start = clint_timer_event_start, - .timer_event_stop = clint_timer_event_stop, - .system_reboot = ariane_system_reboot, - .system_shutdown = ariane_system_shutdown -}; - -const struct sbi_platform platform = { - .opensbi_version = OPENSBI_VERSION, - .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), - .name = "ARIANE RISC-V", - .features = SBI_ARIANE_FEATURES, - .hart_count = ARIANE_HART_COUNT, - .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, - .platform_ops_addr = (unsigned long)&platform_ops -}; diff --git a/platform/fpga/ariane/config.mk b/platform/fpga/ariane/config.mk new file mode 100644 index 00000000..3556461a --- /dev/null +++ b/platform/fpga/ariane/config.mk @@ -0,0 +1,36 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2019 FORTH-ICS/CARV +# Panagiotis Peristerakis +# + +#for more infos, check out /platform/template/config.mk + +PLATFORM_RISCV_XLEN = 64 + +# Blobs to build +FW_TEXT_START=0x80000000 +FW_JUMP=n + +ifeq ($(PLATFORM_RISCV_XLEN), 32) + # This needs to be 4MB aligned for 32-bit support + FW_JUMP_ADDR=0x80400000 + else + # This needs to be 2MB aligned for 64-bit support + FW_JUMP_ADDR=0x80200000 + endif +FW_JUMP_FDT_ADDR=0x82200000 + +# Firmware with payload configuration. +FW_PAYLOAD=y + +ifeq ($(PLATFORM_RISCV_XLEN), 32) +# This needs to be 4MB aligned for 32-bit support + FW_PAYLOAD_OFFSET=0x400000 +else +# This needs to be 2MB aligned for 64-bit support + FW_PAYLOAD_OFFSET=0x200000 +endif +FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_ALIGN=0x1000 diff --git a/platform/fpga/ariane/objects.mk b/platform/fpga/ariane/objects.mk new file mode 100644 index 00000000..814e6da6 --- /dev/null +++ b/platform/fpga/ariane/objects.mk @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2019 FORTH-ICS/CARV +# Panagiotis Peristerakis +# + +platform-objs-y += platform.o diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c new file mode 100644 index 00000000..bba04d63 --- /dev/null +++ b/platform/fpga/ariane/platform.c @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2019 FORTH-ICS/CARV + * Panagiotis Peristerakis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARIANE_UART_ADDR 0x10000000 +#define ARIANE_UART_FREQ 50000000 +#define ARIANE_UART_BAUDRATE 115200 +#define ARIANE_UART_REG_SHIFT 2 +#define ARIANE_UART_REG_WIDTH 4 +#define ARIANE_PLIC_ADDR 0xc000000 +#define ARIANE_PLIC_NUM_SOURCES 3 +#define ARIANE_HART_COUNT 1 +#define ARIANE_CLINT_ADDR 0x2000000 +#define PLIC_ENABLE_BASE 0x2000 +#define PLIC_ENABLE_STRIDE 0x80 +#define PLIC_CONTEXT_BASE 0x200000 +#define PLIC_CONTEXT_STRIDE 0x1000 + +#define SBI_ARIANE_FEATURES \ + (SBI_PLATFORM_HAS_TIMER_VALUE | \ + SBI_PLATFORM_HAS_SCOUNTEREN | \ + SBI_PLATFORM_HAS_MCOUNTEREN | \ + SBI_PLATFORM_HAS_MFAULTS_DELEGATION) + + +/* + * Ariane platform early initialization. + */ +static int ariane_early_init(bool cold_boot) +{ + /* For now nothing to do. */ + return 0; +} + +/* + * Ariane platform final initialization. + */ +static int ariane_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt = sbi_scratch_thishart_arg1_ptr(); + fdt_fixups(fdt); + + return 0; +} + +/* + * Initialize the ariane console. + */ +static int ariane_console_init(void) +{ + return uart8250_init(ARIANE_UART_ADDR, + ARIANE_UART_FREQ, + ARIANE_UART_BAUDRATE, + ARIANE_UART_REG_SHIFT, + ARIANE_UART_REG_WIDTH); +} + +static int plic_ariane_warm_irqchip_init(u32 target_hart, + int m_cntx_id, int s_cntx_id) +{ + size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1; + + if (ARIANE_HART_COUNT <= target_hart) + return -1; + /* By default, enable all IRQs for M-mode of target HART */ + if (m_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(m_cntx_id, i, 1); + } + /* Enable all IRQs for S-mode of target HART */ + if (s_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(s_cntx_id, i, 1); + } + /* By default, enable M-mode threshold */ + if (m_cntx_id > -1) + plic_set_thresh(m_cntx_id, 1); + /* By default, disable S-mode threshold */ + if (s_cntx_id > -1) + plic_set_thresh(s_cntx_id, 0); + + return 0; +} + +/* + * Initialize the ariane interrupt controller for current HART. + */ +static int ariane_irqchip_init(bool cold_boot) +{ + u32 hartid = current_hartid(); + int ret; + + if (cold_boot) { + ret = plic_cold_irqchip_init(ARIANE_PLIC_ADDR, + ARIANE_PLIC_NUM_SOURCES, + ARIANE_HART_COUNT); + if (ret) + return ret; + } + return plic_ariane_warm_irqchip_init(hartid, + 2 * hartid, 2 * hartid + 1); +} + +/* + * Initialize IPI for current HART. + */ +static int ariane_ipi_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_ipi_init(ARIANE_CLINT_ADDR, + ARIANE_HART_COUNT); + if (ret) + return ret; + } + + return clint_warm_ipi_init(); +} + +/* + * Initialize ariane timer for current HART. + */ +static int ariane_timer_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_timer_init(ARIANE_CLINT_ADDR, + ARIANE_HART_COUNT, TRUE); + if (ret) + return ret; + } + + return clint_warm_timer_init(); +} + +/* + * Reboot the ariane. + */ +static int ariane_system_reboot(u32 type) +{ + /* For now nothing to do. */ + sbi_printf("System reboot\n"); + return 0; +} + +/* + * Shutdown or poweroff the ariane. + */ +static int ariane_system_shutdown(u32 type) +{ + /* For now nothing to do. */ + sbi_printf("System shutdown\n"); + return 0; +} + +/* + * Platform descriptor. + */ +const struct sbi_platform_operations platform_ops = { + .early_init = ariane_early_init, + .final_init = ariane_final_init, + .console_init = ariane_console_init, + .console_putc = uart8250_putc, + .console_getc = uart8250_getc, + .irqchip_init = ariane_irqchip_init, + .ipi_init = ariane_ipi_init, + .ipi_send = clint_ipi_send, + .ipi_clear = clint_ipi_clear, + .timer_init = ariane_timer_init, + .timer_value = clint_timer_value, + .timer_event_start = clint_timer_event_start, + .timer_event_stop = clint_timer_event_stop, + .system_reboot = ariane_system_reboot, + .system_shutdown = ariane_system_shutdown +}; + +const struct sbi_platform platform = { + .opensbi_version = OPENSBI_VERSION, + .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), + .name = "ARIANE RISC-V", + .features = SBI_ARIANE_FEATURES, + .hart_count = ARIANE_HART_COUNT, + .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, + .platform_ops_addr = (unsigned long)&platform_ops +}; diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh index 48f8a203..5d7bfb46 100755 --- a/scripts/create-binary-archive.sh +++ b/scripts/create-binary-archive.sh @@ -92,7 +92,7 @@ case "${BUILD_RISCV_XLEN}" in BUILD_PLATFORM_SUBDIR=("qemu/virt") BUILD_PLATFORM_SUBDIR+=("sifive/fu540") BUILD_PLATFORM_SUBDIR+=("kendryte/k210") - BUILD_PLATFORM_SUBDIR+=("ariane-fpga") + BUILD_PLATFORM_SUBDIR+=("fpga/ariane") BUILD_PLATFORM_SUBDIR+=("andes/ae350") BUILD_PLATFORM_SUBDIR+=("thead/c910") BUILD_PLATFORM_SUBDIR+=("spike") -- cgit v1.3.1