From 37b72cb575b26af6b39b0508c0ef8f70dbc0e76f Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Mon, 20 Oct 2025 14:34:14 +0800 Subject: lib: utils/suspend: Add SiFive SMC0 driver The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel --- include/sbi_utils/hsm/fdt_hsm_sifive_tmc0.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/sbi_utils/hsm/fdt_hsm_sifive_tmc0.h (limited to 'include') diff --git a/include/sbi_utils/hsm/fdt_hsm_sifive_tmc0.h b/include/sbi_utils/hsm/fdt_hsm_sifive_tmc0.h new file mode 100644 index 00000000..06cfb390 --- /dev/null +++ b/include/sbi_utils/hsm/fdt_hsm_sifive_tmc0.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 SiFive Inc. + */ + +#ifndef __FDT_HSM_SIFIVE_TMC0_H__ +#define __FDT_HSM_SIFIVE_TMC0_H__ + +int sifive_tmc0_set_wakemask_enareq(u32 hartid); +void sifive_tmc0_set_wakemask_disreq(u32 hartid); +bool sifive_tmc0_is_pg(u32 hartid); + +#endif -- cgit v1.3.1