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<title>rt-thread.git/.travis.yml, branch v4.0.0</title>
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<updated>2019-01-27T06:31:54Z</updated>
<entry>
<title>[ci] remove unnecessary stm32 bsp</title>
<updated>2019-01-27T06:31:54Z</updated>
<author>
<name>BernardXiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-01-27T06:31:54Z</published>
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<entry>
<title>Update .travis.yml for imxrt BSP CI</title>
<updated>2019-01-27T01:17:06Z</updated>
<author>
<name>BernardXiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-01-27T01:17:06Z</published>
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<id>urn:sha1:9e3bccce2ece8766d2d2cc95b7b5f1d0975da672</id>
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<entry>
<title>[bsp][stm32] add stm32g071-st-nucleo ci &amp;&amp; index</title>
<updated>2019-01-22T07:15:17Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2019-01-22T07:13:24Z</published>
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<id>urn:sha1:da3ec767a4c7d131d0c46da9afa59d836682380f</id>
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<entry>
<title>[bsp][stm32] update stm32 bsp ci</title>
<updated>2019-01-19T01:39:35Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2019-01-19T01:39:17Z</published>
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<id>urn:sha1:3b98ff13779e11e4d4f958a318427f83b3c92db7</id>
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<entry>
<title>[bsp][stm32] add new bsp ci</title>
<updated>2019-01-14T10:29:40Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2019-01-14T10:29:20Z</published>
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<entry>
<title>[bsp][stm32] add ci for stm32f411-st-nucleo bsp</title>
<updated>2019-01-08T06:53:38Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2019-01-08T06:53:02Z</published>
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<id>urn:sha1:f39797090309101ccb5150dcadc95befb0cc2b1e</id>
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<entry>
<title>[bsp][stm32] change dir name stm32f091-nucleo to stm32f091-st-nucleo</title>
<updated>2019-01-03T05:42:57Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2019-01-03T05:41:55Z</published>
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<id>urn:sha1:43d88940dfea4a72f02453d6f8fdb1f51a007495</id>
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<entry>
<title>[bsp][stm32] add more stm32 bsp to ci</title>
<updated>2018-12-28T06:35:32Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2018-12-28T06:35:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=8e742404cdbf30b57422dfbee571260d3d605c9d'/>
<id>urn:sha1:8e742404cdbf30b57422dfbee571260d3d605c9d</id>
<content type='text'>
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<entry>
<title>[bsp][STM32] Add CI for new stm32 bsp</title>
<updated>2018-11-29T09:25:59Z</updated>
<author>
<name>SummerGift</name>
<email>SummerGift@qq.com</email>
</author>
<published>2018-11-29T09:10:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=c40bea56b06d54a933478c6d2548836784e8bfb6'/>
<id>urn:sha1:c40bea56b06d54a933478c6d2548836784e8bfb6</id>
<content type='text'>
</content>
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<entry>
<title>Update .travis.yml</title>
<updated>2018-11-10T04:22:25Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2018-11-10T04:22:25Z</published>
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