Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/bsp/Infineon/psoc6-cy8ckit-062-BLE?h=master 2026-09-21T07:44:01Z 2026-09-21T07:44:01Z 萌新源 90902259+mengxinyuan638@users.noreply.github.com 2026-09-21T07:44:01Z urn:sha1:005d2914925308bad929d4e83a0edc1349c4a1b8 * [bsp/Infineon] Fix PWM macro mismatches left by the CHx_PORTy rename Commit e5382cb733 renamed the PWM table guards in drv_pwm.c to the CHx_PORTy convention but only adapted the psoc6-evk Kconfig, leaving several mismatches behind: - The psoc6-evaluationkit-062S2 slider sample still tested the old flat name BSP_USING_PWM0_PORT0 while the board Kconfig defines BSP_USING_PWM0_CH0_PORT0, so the PWM init was compiled out. - The PORT13 entry was renamed to BSP_USING_PWM0_CH7_PORT13, a macro that no Kconfig defines, and the channel is wrong anyway: PWM0_CH3_PORT13_CONFIG carries .channel = 3, PORT13 sits under the PWM0 CH3 menu, and the slider demo selects CH3 + PORT13. - The PSOC62 template and five psoc6 boards (cy8ckit-062-BLE, cy8ckit-062-WIFI-BT, cy8ckit-062S2-43012, cy8ckit-062s4, cy8cproto-062S3-4343W) still define the old flat names. Fix all of them by migrating the evaluationkit sample to BSP_USING_PWM0_CH0_PORT0 and renaming the PORT13 group to BSP_USING_PWM0_CH3_PORT13 across drv_pwm.c, the PSOC62 template and the five boards' Kconfigs/slider samples, so Kconfig, driver table and samples match again. Note: the sibling guards BSP_USING_PWM0_CH7_PORT2/5/7/9/10/12 are still not generated by these boards' Kconfigs; left untouched for a separate discussion. * style: format code with clang-format [skip ci] 2026-07-22T05:32:41Z CYFS 2805686936@qq.com 2026-07-17T05:02:53Z urn:sha1:55cf9cd3fab52a3535691c9cdda44b5581cd9671 2026-07-20T05:05:46Z CYFS 2805686936@qq.com 2026-07-01T07:27:44Z urn:sha1:25212f374583a6f36133809bdd3b6ae51641d083 2026-07-16T05:19:57Z CYFS 2805686936@qq.com 2026-07-15T09:54:33Z urn:sha1:414ff7f3710168dbf99a398e18b2a4ff8448b005 2026-07-09T09:29:51Z CYFS 2805686936@qq.com 2026-06-10T09:13:05Z urn:sha1:dd7da0fd799dd34dd0db781dcfdab7c4b2dedf39 2026-05-08T03:22:12Z CYFS 2805686936@qq.com 2026-05-08T02:47:41Z urn:sha1:4e46e97c18d4cb53b96b57f373137855b641159f 2026-01-31T09:44:27Z Bernard Xiong bernard.xiong@gmail.com 2026-01-31T09:44:27Z urn:sha1:743b614875fc33257be47ab53b6c5e040ec27893 * [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue 2026-01-21T07:21:34Z dongly chinky@163.com 2025-12-19T03:18:43Z urn:sha1:f556099146dd50f770c609711d48e17a201952bc 2025-10-23T14:06:51Z kurisaw 2053731441@qq.com 2025-10-23T02:42:47Z urn:sha1:e2aed47b6c0ef75ead36cae04c4e9afd9d8049aa 2025-06-17T07:42:49Z 沐攸 17773439684@163.com 2025-06-17T07:42:49Z urn:sha1:5f9f5222854f394efee2ed0e99484ca4da1ea591