rt-thread.git/bsp/cvitek/c906_little/board/cache.h, branch copilot/remove-vbus-code-implementationUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/bsp/cvitek/c906_little/board/cache.h?h=copilot%2Fremove-vbus-code-implementation2025-01-16T01:05:52Z[bsp][cvitek] add cache opration functions for cache coherence2025-01-16T01:05:52Zimcuign7798540@gmail.com2024-11-26T06:54:43Zurn:sha1:6cbb2c3ee59c8f46528df89225cf3aa235d46884
By default, the small core enables D-Cache without ensuring cache
coherence. Therefore, when using shared memory, inconsistencies can
occur in the data read by the small core and the big core.
Solution: Migrate cache-related functions from the official
duo-buildroot-sdk library to implement cache-related operations in
rthw.h. This allows you to either disable D-Cache or call the
flush_dcache_range function before reading and after writing for
synchronization.
It is recommended to use the flush_dcache_range function, as disabling
D-Cache can have a significant performance impact.
Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>