rt-thread.git/bsp/cvitek/c906_little, branch copilot/remove-vbus-code-implementation

[format][version]: synchronize bsp version configuration

2025-10-23T14:06:51Z

format: update all series of BSP configuration items (#10406)

2025-06-17T07:42:49Z

bsp: cvitek: c906_littel: fixed build warnings for board.c

2025-01-30T01:28:38Z

When building bsp/cvitek/c906_little, compiler warns: ``` board/board.c: In function 'rt_hw_board_init': board/board.c:26:5: warning: implicit declaration of function 'rt_hw_tick_init'; did you mean 'rt_hw_stack_init'? [-Wimplicit-function-declaration] 26 | rt_hw_tick_init(); | ^~~~~~~~~~~~~~~ | rt_hw_stack_init board/board.c:29:5: warning: implicit declaration of function 'rt_hw_uart_init'; did you mean 'rt_hw_board_init'? [-Wimplicit-function-declaration] 29 | rt_hw_uart_init(); | ^~~~~~~~~~~~~~~ | rt_hw_board_init ``` To remove these build warnings, include header files which declare these functions. Plus, remove the decalartion of `tick_isr()`, this function does not exist. Signed-off-by: Chen Wang

bsp: cvitek: use rttpkgtool to replace cvitek_bootloader

2025-01-26T02:55:44Z

Originally, for riscv big and little cores under bsp/cvitek, after generating rtthread.bin, the cvitek_bootloader tool would be used to package it and generate fip.bin and boot.sd files that can be burned into sdcard. However, the cvitek_bootloader tool repository is relatively large, and it compiles and generates firmware such as fsbl, opensbi and uboot from the source code level. And when using it, it needs to be downloaded to the bsp/cvitek directory, which will introduce pollution to source files in the RTT repository under the original working path. The new solution uses rttpkgtool, which is similar to cvitek_bootloader, but it uses prebuilt firmware, so it is very small and does not introduce pollution to the source file. Signed-off-by: Chen Wang

Revert "[action] add cvitek/c906_little ci" (#9945)

2025-01-23T02:37:56Z

Revert "[action] add cvitek/c906_little ci (#9901)" This reverts commit 969e0e01ef603d3929a186e8bd03f3657ec8227c.

[action] add cvitek/c906_little ci (#9901)

2025-01-23T01:35:06Z

* [action] add cvitek/c906_little ci * Update bsp_buildings.yml * Update rtconfig.py

[bsp][cvitek] fix c906_little build warning in cache.c

2025-01-20T06:26:50Z

build warning: passing argument 1 of 'inv_icache_range' makes integer from pointer without a cast [-Wint-conversion] Analyze: The passed parameter type is void*, which is a pointer type, but the required type is uintptr_t, which is an integer type. Therefore, there will be a 'makes integer from pointer without a cast' warning. Solution: casting the void* pointer to uintptr_t, ensure that the function receives the correct type. Signed-off-by: zdtyuiop4444

bsp/cvitek: print arch info. during boot-up (#9919)

2025-01-16T14:33:55Z

Duo's CPU combination is more complicated: | BSP | B/L core| ISA | UART | | ------------- | ------- |---------------- |-------| | cv18xx_risc-v | Big | RISC-V C906 | UART0 | | c906-little | Littel | RISC-V C906 | UART1 | | cv18xx_aarch64| Big | ARM Cortex A53 | UART0 | Printing ISA and big and small core information during the boot process helps developers/testers determine the CPU and serial port corresponding to the current console. In addition, the RTT logo printing has already distinguished whether it is smart, so the bsp printing no longer distinguishes. Updated README to sync with this change. Signed-off-by: Chen Wang

[bsp][cvitek] add cache opration functions for cache coherence

2025-01-16T01:05:52Z

By default, the small core enables D-Cache without ensuring cache coherence. Therefore, when using shared memory, inconsistencies can occur in the data read by the small core and the big core. Solution: Migrate cache-related functions from the official duo-buildroot-sdk library to implement cache-related operations in rthw.h. This allows you to either disable D-Cache or call the flush_dcache_range function before reading and after writing for synchronization. It is recommended to use the flush_dcache_range function, as disabling D-Cache can have a significant performance impact. Signed-off-by: zdtyuiop4444

bsp: cvitek: fix bug in setting PLIC_PRIORITY[n]

2025-01-16T01:03:26Z

description: In the bsp/cvitek/c906_little/board/interrupt.c, There is an issue with setting the PLIC_PRIORITY[n]. analysis: PLIC_PRIORITY[n] each register corresponds to the priority of a hardware interrupt number. Solution: Each register is 4 bytes. Multiply the total number of IRQs by 4 instead of dividing by 4. Signed-off-by: Liu Gui