rt-thread.git/bsp/cvitek/cv18xx_risc-v/board, branch copilot/fix-format-string-injection

[components][clock_time] Refactor time subsystem around clock_time (#11111)

2026-01-31T09:44:27Z

* [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue

bsp: cvitek: riscv: use marco for linker script

2025-04-22T01:48:53Z

Regarding link script, some memory offsets and sizes are different between the standard version and the smart version (such as "__STACKSIZE__", kernel start address, kernel memory size, etc.). Original solution is replacing link scripts and use INCLUDE, which is relatively complicated. This improvement uses macros to replace constants in the link script. The preprocessing mechanism provided by gcc is used to dynamically replace constant values during the build process. In addition, the kernel load address (the corresponding KERNEL_VADDR_START for smart) was originally configured as 0xFFFFFFC000200000, which is default value of riscv with kernelmap enabled (0xffffffc000000000) plus offset to skip over bootloader (0x200000). This caused a trouble: due to default bsp configuration is for smart, if we switched to the standard version and build, and then switched back to the smart version, the value of KERNEL_VADDR_START will be default back to 0xffffffc000000000, which is different from the original configuration value, resulting in the need to manually reconfigure it, which is easy to forget and cause problems. The current solution is to use the default value 0xffffffc000000000 in the configuration. Add offset to the code and link script when using it. This patch update the default .config and rtconfig.h for cv18xx_riscv. Signed-off-by: Chen Wang

support milkv-duo rt-smart

2024-11-25T02:48:36Z

1. switches memory management to SLA 2. use ioremap modification driver Signed-off-by: flyingcys flyingcys@163.com

bsp: cvitek: Add timer driver

2024-08-25T16:11:57Z

Signed-off-by: Shicheng Chu <1468559561@qq.com>

bsp: cvitek: Canonically rename some macro definitions

2024-08-20T01:52:18Z

Analysis: Some macro definition names are not standardized and lack prefixes. Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE. Signed-off-by: Shicheng Chu <1468559561@qq.com>

bsp: enable KERNEL_REMAP for cvitek platform

2024-07-29T12:18:19Z

Changes: - board.c: add static assert for KERNEL_VADDR_START to check if it's valid - board.h: updated deafult KERNEL_VADDR_START for standard version - config bsp for v5.2.0 smart requirements - kconfig: update bsp Kconfig for remap kernel Signed-off-by: Shell Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229 Reviewed-by: Chen Wang

bsp:cvitek: add pinmux for adc

2024-07-16T10:29:17Z

Signed-off-by: Chen Wang

bsp:cvitek: add pinmux for spi

2024-07-16T10:29:17Z

Board level pin available info: duo & duo256: NAME SPI CV1800B/GPIO __ ---- --- ------------ --------------------- GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X Signed-off-by: Chen Wang

bsp:cvitek: add pinmux for pwm

2024-07-16T10:29:17Z

Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang

bsp:cvitek: add pinmux for uart

2024-07-16T10:29:17Z

Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang