rt-thread.git/bsp/cvitek/cv18xx_risc-v, branch copilot/fix-format-string-injection

[components][clock_time] Refactor time subsystem around clock_time (#11111)

2026-01-31T09:44:27Z

* [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue

[format][version]: synchronize bsp version configuration

2025-10-23T14:06:51Z

bsp/cvitek: Increase the value of RT_NAME_MAX

2025-09-25T05:03:00Z

Otherwise report runtime error: [E/kernel.obj] Object name sys workq exceeds RT_NAME_MAX=8, consider increasing RT_NAME_MAX. (obj_name_len <= RT_NAME_MAX - 1) assertion failed at function:rt_object_allocate, line number:520 Increase the value of RT_NAME_MAX to 16 for c906B. The value of RT_NAME_MAX for BSP of C906L and ARM core already meet the requirement of more than 8. Signed-off-by: Chen Wang

format: update all series of BSP configuration items (#10406)

2025-06-17T07:42:49Z

bsp: cvitek: riscv: use marco for linker script

2025-04-22T01:48:53Z

Regarding link script, some memory offsets and sizes are different between the standard version and the smart version (such as "__STACKSIZE__", kernel start address, kernel memory size, etc.). Original solution is replacing link scripts and use INCLUDE, which is relatively complicated. This improvement uses macros to replace constants in the link script. The preprocessing mechanism provided by gcc is used to dynamically replace constant values during the build process. In addition, the kernel load address (the corresponding KERNEL_VADDR_START for smart) was originally configured as 0xFFFFFFC000200000, which is default value of riscv with kernelmap enabled (0xffffffc000000000) plus offset to skip over bootloader (0x200000). This caused a trouble: due to default bsp configuration is for smart, if we switched to the standard version and build, and then switched back to the smart version, the value of KERNEL_VADDR_START will be default back to 0xffffffc000000000, which is different from the original configuration value, resulting in the need to manually reconfigure it, which is easy to forget and cause problems. The current solution is to use the default value 0xffffffc000000000 in the configuration. Add offset to the code and link script when using it. This patch update the default .config and rtconfig.h for cv18xx_riscv. Signed-off-by: Chen Wang

修复 MMCSD 宏拼写错误+内核开启LOG_D编译问题

2025-03-12T08:02:43Z

bsp: cvitek: removed useless files after using rttpkgtool

2025-01-26T02:55:44Z

Based on the patch "bsp: cvitek: use rttpkgtool to replace cvitek_bootloader", continue cleanup useless files. Signed-off-by: Chen Wang

bsp: cvitek: use rttpkgtool to replace cvitek_bootloader

2025-01-26T02:55:44Z

Originally, for riscv big and little cores under bsp/cvitek, after generating rtthread.bin, the cvitek_bootloader tool would be used to package it and generate fip.bin and boot.sd files that can be burned into sdcard. However, the cvitek_bootloader tool repository is relatively large, and it compiles and generates firmware such as fsbl, opensbi and uboot from the source code level. And when using it, it needs to be downloaded to the bsp/cvitek directory, which will introduce pollution to source files in the RTT repository under the original working path. The new solution uses rttpkgtool, which is similar to cvitek_bootloader, but it uses prebuilt firmware, so it is very small and does not introduce pollution to the source file. Signed-off-by: Chen Wang

bsp/cvitek: print arch info. during boot-up (#9919)

2025-01-16T14:33:55Z

Duo's CPU combination is more complicated: | BSP | B/L core| ISA | UART | | ------------- | ------- |---------------- |-------| | cv18xx_risc-v | Big | RISC-V C906 | UART0 | | c906-little | Littel | RISC-V C906 | UART1 | | cv18xx_aarch64| Big | ARM Cortex A53 | UART0 | Printing ISA and big and small core information during the boot process helps developers/testers determine the CPU and serial port corresponding to the current console. In addition, the RTT logo printing has already distinguished whether it is smart, so the bsp printing no longer distinguishes. Updated README to sync with this change. Signed-off-by: Chen Wang

bsp: cvitek: remove support for spinor/spinand

2025-01-08T22:54:14Z

Confirmed with milkv, only the sd card version is sold by default for duo in the market. The spi pins are provided through stamp holes, so that users can solder the corresponding components on their baseboard during secondary development. In order to simplify maintenance work, the mainline will only support the sd-card version and no longer support spinor/spinand. Updated config files the same in this patch. Signed-off-by: Chen Wang