Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/bsp/gd32/arm?h=copilot%2Ffix-format-string-injection 2026-03-04T05:34:12Z 2026-03-04T05:34:12Z ShiHongChao 119155792+ShiHongChao@users.noreply.github.com 2026-03-04T05:34:12Z urn:sha1:196477d7535abee56cd44a958ed6e5be9c266322 * feat(bsp/gd32): 增加GDF405RG芯片BSP * chore(bsp/gd32): 取消git对RTE目录的跟踪，并更新README中的BSP条目 * style(bsp/gd32): 修改格式 2026-03-02T02:33:27Z ShiHongChao 119155792+ShiHongChao@users.noreply.github.com 2026-03-02T02:33:27Z urn:sha1:a10ac694e1886070925e4ff4592f0b0d89956a10 2026-01-31T09:44:27Z Bernard Xiong bernard.xiong@gmail.com 2026-01-31T09:44:27Z urn:sha1:743b614875fc33257be47ab53b6c5e040ec27893 * [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue 2026-01-21T07:21:34Z dongly chinky@163.com 2025-12-19T03:18:43Z urn:sha1:f556099146dd50f770c609711d48e17a201952bc 2025-12-01T06:47:53Z godmial 57511148+godmial@users.noreply.github.com 2025-12-01T06:47:53Z urn:sha1:2fb53c83c5d41fed43f347071ce189f104b2e5d7 * feat(gd32): 优化GD32F470 SPI Flash初始化和UART0配置 主要修改： 1. SPI Flash初始化优化 - 添加可配置的SPI Flash自动初始化选项(BSP_USING_SPI_FLASH) - 支持按SPI总线独立配置Flash初始化(BSP_USING_SPIx_FLASH) - 避免SPI Flash初始化与其他SPI设备(如OLED、WIFI)冲突 - 添加SPI5 Flash支持 - 修改drv_spi_flash.c，仅在明确配置的SPI总线上初始化Flash 2. UART0配置修复 - 将UART0的AFIO默认值从AF1改为AF7 - 修复串口无响应问题 这些修改使得用户可以更灵活地配置SPI Flash初始化，避免自动初始化导致的设备冲突问题。 * feat(gd32): 解耦SPI Flash与SFUD的依赖关系 2025-11-26T13:42:29Z kurisaw 2053731441@qq.com 2025-11-26T06:09:15Z urn:sha1:5706c5ef4db7482168bb05db0c69fc648ae7950e 2025-11-26T13:42:29Z kurisaw 2053731441@qq.com 2025-11-14T02:44:21Z urn:sha1:98b9ecdba69727462ae69a4909cd2e43d3047f36 2025-11-26T13:42:29Z kurisaw 2053731441@qq.com 2025-11-13T09:14:11Z urn:sha1:d32ed6a4afbc65d0be3b1c1683e093cb023627ae 2025-11-08T02:39:25Z RyanCW 75795462+Ryan-CW-Code@users.noreply.github.com 2025-11-08T02:39:25Z urn:sha1:6e184553d12a458b5e24e6243d6fbea00136abf0 2025-11-07T01:28:59Z RyanCW 75795462+Ryan-CW-Code@users.noreply.github.com 2025-11-07T01:28:59Z urn:sha1:97f316f5d0bda09d7b612997e26614bdb7417be3 [bsp][gd32][serial_v2] 增加 GD32F5 支持