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<title>rt-thread.git/bsp/mipssim/rtconfig.py, branch v5.3.0-beta</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/bsp/mipssim/rtconfig.py?h=v5.3.0-beta</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/bsp/mipssim/rtconfig.py?h=v5.3.0-beta'/>
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<updated>2019-12-11T07:25:31Z</updated>
<entry>
<title>[bsp] Add mipssim bsp</title>
<updated>2019-12-11T07:25:31Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2019-12-06T17:02:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=4584054e17e8143b3a09bd6cec63c6a8f2658d06'/>
<id>urn:sha1:4584054e17e8143b3a09bd6cec63c6a8f2658d06</id>
<content type='text'>
This bsp is used for test MIPS base code in simutator,
implemented basic MIPS cpuport and serial port driver.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
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