rt-thread.git/bsp/n32, branch copilot/fix-riscv-none-job-failure

[bsp][n32] n32hxxx: fix H7xx hard I2C abort and add the missing SDK header

2026-09-16T01:06:34Z

The N32H7xx branch of drv_hard_i2c.c had never been compiled. The file takes its peripheral declarations from board.h, and only n32h497zgl7-evb includes n32h49x_i2c.h, so on H7xx every I2C symbol was undefined and the option could not build at all. Include the peripheral header from the driver itself, the way drv_sdram.c already does. I2C_ABORT_ON_TIMEOUT also degraded to a bare `state = I2C_READY` on H7xx, at the four rt_completion_wait() timeouts in n32_i2c_master_xfer(). The H49x implementation is written against the older IP - I2C_ClrIntPendingBit, I2C_STS2_BUSY, I2C_CTRL1_STOPGEN - none of which exist in the H7xx SDK, so give H7xx its own teardown. It disables the interrupt and DMA request sources, disables the DMA channel that would otherwise stay armed against the caller's buffer, releases the bus and clears the status residue. Only flags with a matching INTCLR bit may be passed to I2C_ClrFlag(), which is a plain "INTCLR |= flag" write; TFC (0x40) and BUSY (0x8000) have none. I2C_Configuration() was called from n32_i2c_init() but defined nowhere in the tree. It is a board hook for pin mux, which is not the driver's job - the H49x path configures no pins either - so drop the call. Verified by building n32h760zil7-stb with BSP_USING_HARD_I2C1 and its TX/RX DMA enabled, which now compiles and links with no warnings, and n32h497zgl7-evb with I2C1/I2C2 DMA enabled, whose image size is unchanged. Neither board routes I2C pins yet, so this is build-verified only, not hardware-verified.

[bsp][n32] n32h497zgl7-evb: add SDRAM port and correct Kconfig defaults

2026-09-16T01:06:34Z

drv_sdram.c includes unconditionally under BSP_USING_SDRAM, and n32h497zgl7-evb had no such header, so the option could not build at all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16 bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at 0x98000000. The timing values are the ones validated on this board in hardware. Three of the Kconfig defaults described a different part: BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16 BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8 BSP_SDRAM_SIZE default 32 -> 8 BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged. Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile and link with no warnings.

[bsp][n32] n32hxxx: bound the XSPI waits and fix I2C/SPI/NAND edge cases

2026-09-16T01:06:34Z

- qspi: both XSPI variants poll the status flags with no bound, so an unresponsive bus hangs the caller and silently defeats the timeout it passed in. Route every wait through the timeout-carrying helpers, return -RT_ETIMEOUT and disable the controller on failure, and replace the "poll then send" loops with one bounded wait per element. - hard_i2c: the interrupt receive path programs the BYTENUM window once and never reloads it, so a longer message was truncated and still reported as success; refuse it with -RT_EINVAL (enable RX DMA for longer reads) instead of capping XferSize. Stop capping the transmit byte count at the window size as well: BYTENUM counts received bytes only, and the cap stopped feeding DAT after byte 255 while TXDATE stayed asserted. Reject RT_I2C_NO_START/RT_I2C_NO_STOP on the series without frame chaining, where they would silently become a fresh START and a STOP, and tear the DMA channel down when the address phase times out instead of leaving it armed against a buffer about to unwind. - spi: the H7xx LLI chain advanced the memory side by SPI_DMA_BLOCK_MAX bytes although BlkTfrSize counts elements, so a 16-bit transfer walked half a word early per node; advance by elements and scale both the chunk offset and the staging buffer by the data width. Propagate the DMA arm failure that was ignored. - nand: an odd data length has no halfword-only encoding on the 16-bit bus and padding would program a byte the caller never asked for, so refuse it before the command phase; issue the empty-page dummy store as a halfword there too, where 8-bit AHB writes are unsupported. - Kconfig: gate the Ethernet/SDRAM/LCD/QSPI/NAND options behind BSP_PERIPH_PIN_CFG_READY on all three boards. The peripheral clock and IO are not configured for these boards yet, so selecting one of them builds a driver whose pins stay in the reset function.

[bsp][n32] n32hxxx: extend H47x_48x/H49x/H7xx driver support

2026-09-16T01:06:34Z

- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the h47x_48x, h49x and h7xx series, and extend the shared drivers (adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt). - n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing, phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and the IAR/Keil project files. - n32h760zil7-stb: update Kconfig and rtconfig. - CI: register the three n32hxxx boards.

[bsp][n32] add H47X/H49X/H7XX driver support- #11711 #11711

2026-08-20T09:32:18Z

[bsp/n32]上传Nsing LCDC和SDRAM的驱动#11682

2026-08-12T07:37:21Z

[bsp/n32]n32h760zil7-stb bsp修复完善，添加 n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627)

2026-07-22T09:06:34Z

1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry 2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设 3、添加n32h487zgl7-evb初版BSP 4、添加n32h497zgl7-evb初版BSP 5、删除n32g452xx这个bsp --------- Co-authored-by: OnlyoutzZ

[bsp] Place SConscript outputs under build directories

2026-07-22T05:32:41Z

fix: name anonymous Kconfig choices

2026-07-20T05:05:46Z

[bsp][drivers][soft_i2c] unify the software I2C driver

2026-07-16T05:19:57Z