rt-thread.git/bsp/qemu-virt64-riscv/applications, branch master

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

[risc-v][vector] Restore vstart after vector configuration

2026-10-14T01:13:49Z

feat: bsp: qemu-riscv64: using klibc API for printf

2024-09-01T19:12:34Z

[time]时钟框架重构 (#7794)

2023-07-17T12:11:58Z

format Kconfig and sconscript

2023-01-09T03:52:13Z

[rt-smart] kernel virtual memory management layer (#6809)

2023-01-09T02:08:55Z

synchronize virtual memory system works. adding kernel virtual memory management layer for page-based MMU enabled architecture porting libcpu MMU codes porting lwp memory related codes

[smart][risc-v/libcpu] port rv64 cpu code (#6704)

2022-12-10T14:16:42Z

* [risc-v/libcpu] porting Smart & RTOS * [fix] rv64 plic * [risc-v/rv64] remove macro in rtdef

sync branch rt-smart. (#6641)

2022-12-03T04:07:44Z

* Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 Co-authored-by: zhkag

[bsp] rename qemu-riscv-virt64 to qemu-virt64-riscv

2022-05-25T02:05:23Z