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<title>rt-thread.git/bsp/qemu-virt64-riscv/rtconfig.h, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/bsp/qemu-virt64-riscv/rtconfig.h?h=v5.0.2</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/bsp/qemu-virt64-riscv/rtconfig.h?h=v5.0.2'/>
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<updated>2023-10-08T03:21:00Z</updated>
<entry>
<title>[project] update mdk/iar project and config.</title>
<updated>2023-10-08T03:21:00Z</updated>
<author>
<name>guozhanxin</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2023-10-08T03:01:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=9e79333512c445a5202dc040176036bca8e7f8ad'/>
<id>urn:sha1:9e79333512c445a5202dc040176036bca8e7f8ad</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[time]时钟框架重构 (#7794)</title>
<updated>2023-07-17T12:11:58Z</updated>
<author>
<name>xqyjlj</name>
<email>xqyjlj@126.com</email>
</author>
<published>2023-07-17T12:11:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=0eb75ced70a514051fcc6a8f1d232e195b15b4a0'/>
<id>urn:sha1:0eb75ced70a514051fcc6a8f1d232e195b15b4a0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Drivers: Support Open Firmware API and model of PIC</title>
<updated>2023-07-05T08:45:16Z</updated>
<author>
<name>wusongjie</name>
<email>wusongjie@rt-thread.com</email>
</author>
<published>2023-07-05T05:50:18Z</published>
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<id>urn:sha1:8aa4366cb2910c2c61729608d9f2a90868d16deb</id>
<content type='text'>
We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.

Signed-off-by: GuEe-GUI &lt;GuEe-GUI@github.com&gt;
</content>
</entry>
<entry>
<title>sync and update all projects (#7138)</title>
<updated>2023-03-31T08:49:48Z</updated>
<author>
<name>yangjie11</name>
<email>39754270+yangjie11@users.noreply.github.com</email>
</author>
<published>2023-03-31T08:49:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=95e6b69b8e56f86ac8a6d6718a16d255527e87cf'/>
<id>urn:sha1:95e6b69b8e56f86ac8a6d6718a16d255527e87cf</id>
<content type='text'>
* sync and update</content>
</entry>
<entry>
<title>Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901)</title>
<updated>2023-02-05T17:11:04Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2023-02-05T17:11:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=98e0c58527664ae645920729663f0bead1b3dc3f'/>
<id>urn:sha1:98e0c58527664ae645920729663f0bead1b3dc3f</id>
<content type='text'>
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT</content>
</entry>
<entry>
<title>[rt-smart] porting c906 and D1s to mm (#6848)</title>
<updated>2023-01-16T00:24:03Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-16T00:24:03Z</published>
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<id>urn:sha1:f0dadcb3c390e60463afa5892d2d65e6033d82c8</id>
<content type='text'>
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart][risc-v/libcpu] port rv64 cpu code (#6704)</title>
<updated>2022-12-10T14:16:42Z</updated>
<author>
<name>Shell</name>
<email>maschareno@outlook.com</email>
</author>
<published>2022-12-10T14:16:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e991be9c51c54883b56ee3d9e7f30db33c404192'/>
<id>urn:sha1:e991be9c51c54883b56ee3d9e7f30db33c404192</id>
<content type='text'>
* [risc-v/libcpu] porting Smart &amp; RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>update the project for RT-Thread_V4.1.1</title>
<updated>2022-08-16T11:38:48Z</updated>
<author>
<name>liuxianliang</name>
<email>liuxianliang@rt-thread.com</email>
</author>
<published>2022-08-16T07:28:03Z</published>
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<id>urn:sha1:a4eb64b873a9b385ea2eb4d3ab43e9f642f484a6</id>
<content type='text'>
</content>
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