rt-thread.git/bsp/renesas/libraries, branch masterUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/bsp/renesas/libraries?h=master2026-10-11T08:11:07Z[components][libc] run .init_array constructors in cplusplus_system_init2026-10-11T08:11:07Zseteirochenmoushun@163.com2026-10-10T12:34:34Zurn:sha1:3577e7a6ed0f183534e207179de5251e155fd49e
Newer GCC emits C++ global constructors into .init_array, which many
linker scripts keep outside [__ctors_start__, __ctors_end__), so they
never ran. Walk __init_array_start/__init_array_end (weak) as well,
skipping entries already covered by the ctors range.
Add RT_USING_CPP_CRT_INIT for ports whose startup runtime already runs
.init_array, default on for the simulator. With it set, only the
.init_array walk is skipped; the ctors range is still walked.
Renesas RA/RA_WIRELESS/RZ families select it when C++ is enabled: FSP
SystemInit() already walks .init_array, so boards whose linker script
only provides __init_array_* would run constructors twice. Boards that
fold .init_array into the ctors range (ra6m3-hmi-board, ra8d1, rz)
still run them once via RT-Thread.
Also source env.sh and restore RTT_EXEC_PATH in ToolsCI project generate
and dist steps so scons is on PATH (exit 127) and the ARM toolchain path
is not overwritten by env.sh.
Fixes #11778
style: format code with clang-format [skip ci]2026-09-10T08:23:49ZCYFS3128660807+CYFS3@users.noreply.github.com2026-09-10T02:31:08Zurn:sha1:5b8e188af2a5e5aa280db13d23dbe1a9eab8b188[bsp/renesas][drivers] Fix SCI SPI runtime configuration and transfer errors2026-09-10T08:23:49ZCYFS2805686936@qq.com2026-09-09T09:21:48Zurn:sha1:8f8eb450149f745769b7f44aa82da4b3536c229f
修复 SCI SPI 分频参数和运行时配置生命周期，保持位宽单位一致，应用模式及片选配置，并在收发超时或错误后停止传输、清理状态。
[bsp/renesas][drivers] Read PWM settings from GPT registers2026-09-09T02:33:04ZCYFS2805686936@qq.com2026-08-26T02:27:33Zurn:sha1:d7ea2bce99c4dc1e63b28638674e1b94d1791417[bsp/renesas][drivers] Support configurable CAN FD operation2026-09-01T01:16:54ZCYFS2805686936@qq.com2026-08-25T07:39:43Zurn:sha1:7a2af55ffb3632b73ebfc29f01bf9889ed9d1979[BSP][Renesas] Trigger SDHI card detection on R7FA8M852026-08-27T03:48:49ZCYFS2805686936@qq.com2026-08-26T07:28:17Zurn:sha1:5abbbec42022a9a28f060a7fc29d68d1f71e2d3f[bsp/renesas][drivers] Fix SPI runtime configuration2026-08-27T01:01:32ZCYFS2805686936@qq.com2026-08-24T09:58:55Zurn:sha1:69c26789fdec08180960e4091e5d9f9803b75948[bsp/renesas][drivers] Skip invalid chip select writes in SCI SPI2026-08-27T01:01:32ZCYFS2805686936@qq.com2026-08-24T09:52:54Zurn:sha1:fcc4d6c01a9f98270b99de5d9d29a93cfd98331dfix ra6w1 device bug2026-08-21T05:10:01Zrcitachyearsince@yeah.net2026-08-17T08:51:28Zurn:sha1:46d74447738b2f9fc762b5b305ef1ec1f69e61f5feat(renesas): add RA8P1 GPIO and external IRQ DM drivers2026-08-12T04:54:50ZRbb666zhangbingru@rt-thread.com2026-07-31T07:23:24Zurn:sha1:abce28f15cc868f72d0d1f2bfc7e46343869e6d6
Add M85 device-tree GPIO and external-interrupt controllers, IRQ20 FSP integration, built-in DTB support, and BSP usage documentation.