<feed xmlns='http://www.w3.org/2005/Atom'>
<title>rt-thread.git/bsp/rockchip/rk3568/driver, branch copilot/remove-vbus-code-implementation</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/bsp/rockchip/rk3568/driver?h=copilot%2Fremove-vbus-code-implementation</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/bsp/rockchip/rk3568/driver?h=copilot%2Fremove-vbus-code-implementation'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2023-12-09T22:45:14Z</updated>
<entry>
<title>[bsp][rk3568] 修改串口波特率 (#8346)</title>
<updated>2023-12-09T22:45:14Z</updated>
<author>
<name>fangjianzhou</name>
<email>73834245+fangjianzhou@users.noreply.github.com</email>
</author>
<published>2023-12-09T22:45:14Z</published>
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<id>urn:sha1:25bb80b65739e28ec3de7abd2ea6c2a18586d269</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][aarch64] 使用设备树对CPU进行初始化 (#8221)</title>
<updated>2023-11-28T06:20:11Z</updated>
<author>
<name>fangjianzhou</name>
<email>73834245+fangjianzhou@users.noreply.github.com</email>
</author>
<published>2023-11-28T06:20:11Z</published>
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<id>urn:sha1:249871cbbcdc14f1c16a2d502639780ebc6ae078</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[BSP/rockchip/rk3568] fixup heapmem init flow</title>
<updated>2023-09-19T02:27:19Z</updated>
<author>
<name>GuEe-GUI</name>
<email>GuEe-GUI@github.com</email>
</author>
<published>2023-09-15T01:51:10Z</published>
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<id>urn:sha1:a6e9c386ff9a3339ce78eb4aafc61389f2109b26</id>
<content type='text'>
In RT-Smart, `rt_hw_interrupt_init` will call
`rt_ioremap` to map GIC's MMIO registers. There
is a `rt_malloc` called in rt_ioremap, that will
fail if we not init the mem heap yet.

Signed-off-by: GuEe-GUI &lt;GuEe-GUI@github.com&gt;
</content>
</entry>
<entry>
<title>rt_hw_cpu_shutdown: implement default weak function</title>
<updated>2023-08-09T02:34:25Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-08-07T16:42:10Z</published>
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<id>urn:sha1:c6a2f5b7bdee378cc868ee9284e760ebbdf635f0</id>
<content type='text'>
and remvoe duplicated default functions in each cpu/bsp level
</content>
</entry>
<entry>
<title>更新rk3568 bsp 支持PSCI、amp模式</title>
<updated>2023-06-12T01:41:37Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-06-05T05:28:58Z</published>
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<id>urn:sha1:edaa0d9c8a53b1f9b0be71e47074f00044906de5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
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<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722)</title>
<updated>2022-03-29T03:08:25Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-03-29T03:08:25Z</published>
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<id>urn:sha1:f587a55bc2006f4316383425d518b734e42bb4a2</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align

* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568</content>
</entry>
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