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<title>rt-thread.git/bsp/rockchip/rk3568, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/bsp/rockchip/rk3568?h=v5.0.2</id>
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<updated>2023-10-08T03:21:00Z</updated>
<entry>
<title>[project] update mdk/iar project and config.</title>
<updated>2023-10-08T03:21:00Z</updated>
<author>
<name>guozhanxin</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2023-10-08T03:01:28Z</published>
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<id>urn:sha1:9e79333512c445a5202dc040176036bca8e7f8ad</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[BSP/rockchip/rk3568] fixup heapmem init flow</title>
<updated>2023-09-19T02:27:19Z</updated>
<author>
<name>GuEe-GUI</name>
<email>GuEe-GUI@github.com</email>
</author>
<published>2023-09-15T01:51:10Z</published>
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<id>urn:sha1:a6e9c386ff9a3339ce78eb4aafc61389f2109b26</id>
<content type='text'>
In RT-Smart, `rt_hw_interrupt_init` will call
`rt_ioremap` to map GIC's MMIO registers. There
is a `rt_malloc` called in rt_ioremap, that will
fail if we not init the mem heap yet.

Signed-off-by: GuEe-GUI &lt;GuEe-GUI@github.com&gt;
</content>
</entry>
<entry>
<title>rt_hw_cpu_shutdown: implement default weak function</title>
<updated>2023-08-09T02:34:25Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-08-07T16:42:10Z</published>
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<id>urn:sha1:c6a2f5b7bdee378cc868ee9284e760ebbdf635f0</id>
<content type='text'>
and remvoe duplicated default functions in each cpu/bsp level
</content>
</entry>
<entry>
<title>Drivers: Support Open Firmware API and model of PIC</title>
<updated>2023-07-05T08:45:16Z</updated>
<author>
<name>wusongjie</name>
<email>wusongjie@rt-thread.com</email>
</author>
<published>2023-07-05T05:50:18Z</published>
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<id>urn:sha1:8aa4366cb2910c2c61729608d9f2a90868d16deb</id>
<content type='text'>
We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.

Signed-off-by: GuEe-GUI &lt;GuEe-GUI@github.com&gt;
</content>
</entry>
<entry>
<title>更新rk3568 bsp 支持PSCI、amp模式</title>
<updated>2023-06-12T01:41:37Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-06-05T05:28:58Z</published>
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<id>urn:sha1:edaa0d9c8a53b1f9b0be71e47074f00044906de5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>sync and update all projects (#7138)</title>
<updated>2023-03-31T08:49:48Z</updated>
<author>
<name>yangjie11</name>
<email>39754270+yangjie11@users.noreply.github.com</email>
</author>
<published>2023-03-31T08:49:48Z</published>
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<id>urn:sha1:95e6b69b8e56f86ac8a6d6718a16d255527e87cf</id>
<content type='text'>
* sync and update</content>
</entry>
<entry>
<title>Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901)</title>
<updated>2023-02-05T17:11:04Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2023-02-05T17:11:04Z</published>
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<id>urn:sha1:98e0c58527664ae645920729663f0bead1b3dc3f</id>
<content type='text'>
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT</content>
</entry>
<entry>
<title>modify RT_ALIGN_SIZE as 8 by default</title>
<updated>2023-01-13T03:47:23Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-12T04:25:57Z</published>
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<id>urn:sha1:ddccef3a64f1dc477134d4ff73117a653955a5eb</id>
<content type='text'>
</content>
</entry>
<entry>
<title>format link scripts</title>
<updated>2023-01-09T03:52:13Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-09T02:16:47Z</published>
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<id>urn:sha1:592284c66c8a93270cb77cb2a0afb36b64d2bc51</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
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