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<title>rt-thread.git/bsp/rockchip, branch serialX-dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/bsp/rockchip?h=serialX-dev</id>
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<updated>2023-02-05T17:11:04Z</updated>
<entry>
<title>Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901)</title>
<updated>2023-02-05T17:11:04Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2023-02-05T17:11:04Z</published>
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<id>urn:sha1:98e0c58527664ae645920729663f0bead1b3dc3f</id>
<content type='text'>
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT</content>
</entry>
<entry>
<title>modify RT_ALIGN_SIZE as 8 by default</title>
<updated>2023-01-13T03:47:23Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-12T04:25:57Z</published>
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<id>urn:sha1:ddccef3a64f1dc477134d4ff73117a653955a5eb</id>
<content type='text'>
</content>
</entry>
<entry>
<title>format link scripts</title>
<updated>2023-01-09T03:52:13Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-09T02:16:47Z</published>
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<id>urn:sha1:592284c66c8a93270cb77cb2a0afb36b64d2bc51</id>
<content type='text'>
</content>
</entry>
<entry>
<title>format Kconfig and sconscript</title>
<updated>2023-01-09T03:52:13Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-09T02:14:23Z</published>
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<id>urn:sha1:9bc68d26a446158aad13f910fa5a2b8b09febec1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
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<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[rtdef] use lower-case to define attributes (#6728)</title>
<updated>2022-12-11T18:12:03Z</updated>
<author>
<name>Man, Jianting (Meco)</name>
<email>920369182@qq.com</email>
</author>
<published>2022-12-11T18:12:03Z</published>
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<id>urn:sha1:99bdf978d7fe4ec18ed50a639e15b254825c871b</id>
<content type='text'>
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ecf2d8215961ca7c539132b62a72df6072cc3e14'/>
<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>[bsp][readme] 增加scons --exec-path=xxx 命令的使用说明</title>
<updated>2022-10-10T01:42:44Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2022-10-09T23:08:19Z</published>
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<id>urn:sha1:8b0610fc349755b69f3952359054964410d848e4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp][applications][sconscript] 整理统一sconscript格式 (#6481)</title>
<updated>2022-10-03T14:43:08Z</updated>
<author>
<name>Man, Jianting (Meco)</name>
<email>920369182@qq.com</email>
</author>
<published>2022-10-03T14:43:08Z</published>
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<id>urn:sha1:f7be5fc84b934dfe588acd947fb75abc6833fde8</id>
<content type='text'>
* [bsp][sconscript] 整理统一sconscript格式

* update

* update</content>
</entry>
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