rt-thread.git/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c, branch masterUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c?h=master2026-09-16T01:05:27Z[bsp][stm32] Add stm32n657-st-nucleo BSP (#11799)2026-09-16T01:05:27Zyans6666103115555+yans6666@users.noreply.github.com2026-09-16T01:05:27Zurn:sha1:1d2152ceeefef23dba61e80d97f0f4e20d46dd05
* [bsp][stm32] Add stm32n657-st-nucleo BSP
* style: format STM32 HAL drivers and STM32N657 BSP with clang-format[bsp][stm32] Add SPI BDMA support and unify DMA/BDMA/GPDMA config2026-09-14T01:59:27Zmoment-NEWcghdudu@qq.com2026-09-11T05:24:33Zurn:sha1:ca73422bd66a9ba57850a297e232d111d2cd85a1
- Unify DMA/BDMA/GPDMA descriptors in drv_dma (common fields + per-type union)
- Support BDMA in SPI driver with h7 dma/spi config header updates
- Add SPI6 TX/RX BDMA Kconfig options for H7
fix[STM32][SPI]: keep async route decision stable per message2026-06-15T06:46:35Zwdfk-prog1425075683@qq.com2026-06-12T02:32:15Zurn:sha1:67a90eb94080e16cc2281654cacffa61fc07aa64
snapshot scheduler and interrupt state once per SPI message
reuse the message-level async route decision for all split chunks
disable DMA and interrupt paths consistently when async transfer is unavailable
avoid mixed async and polling policies within one logical SPI transfer
fix[STM32][SPI]: preload receive-only dummy buffer2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-18T08:02:59Zurn:sha1:3fa50a4b33869050ca8f17e5162b397fddf3e5bf
preload the actual HAL receive buffer with 0xFF for receive-only transfers
rename spi_dma_flag to spi_xfer_flags to match DMA and interrupt flags
clarify SPI async completion and transfer-mode comments
add Doxygen comments for STM32 SPI runtime structures and handlers
fix[STM32][SPI]: ignore benign Tx-only OVR after async completion2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-11T02:44:47Zurn:sha1:bdcaf2ad5633b4bb4231d14189c24a60cc40c0b7feat[STM32][SPI]: add interrupt transfer scaffolding for spi driver2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-06T13:02:37Zurn:sha1:415f924c5fb08b03a9b3a5a5ef63a1a7705378b3
introduce interrupt transfer route selection and SPI IRQ visibility macros
unify DMA and INT completion handling with timeout-triggered abort recovery
keep short transfers on polling and use DMA or INT only when eligible
refine STM32 SPI init and IRQ registration paths for mixed transfer backends
feat[STM32][SPI]: refine dma config hierarchy for hard spi2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-04-15T02:53:21Zurn:sha1:e37e3107f4bb18a06f4b922032345a2e1938f893
refine the stm32 hard spi dma configuration hierarchy with shared feature macros
align dma flag usage with rt-device dma flags and gate dma-only fields and paths
make the dma transfer threshold configurable through BSP_SPI_DMA_TRANS_MIN_LEN
refactor[STM32][DMA]: add common DMA helper layer for HAL drivers2026-05-06T07:30:39Zwdfk-prog1425075683@qq.com2026-05-05T01:06:22Zurn:sha1:c45f5f926725d521db3a438117688c2011c0bed6
- add drv_dma common helpers and stm32_dma_config descriptors for STM32 series
- refactor i2c, spi, usart, qspi, and sdio DMA setup and deinit paths to reuse the common layer
- unify DMA IRQ enable, rollback handling, and const board-level DMA configuration usage
Fix SPI DMA timeout units and free temporary buffers2026-04-19T03:19:07Zwdfk-prog1425075683@qq.com2026-03-06T08:10:28Zurn:sha1:b0e55a46a1d58cadde8f2bbd4afe67a95cdc9368fix:[STM32][SPI]Refactor spixfer to fix DMA reception bug, correct timeout calculation2026-04-19T03:19:07Zwdfk-prog1425075683@qq.com2026-03-06T08:08:42Zurn:sha1:d9ff39eec22212f36e4ee6437a2a84b1d1d82489