rt-thread.git/bsp/stm32, branch copilot/fix-aarch64-github-actions-jobUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/bsp/stm32?h=copilot%2Ffix-aarch64-github-actions-job2026-06-02T10:06:01ZFix BSP dist packaging2026-06-02T10:06:01ZCYFS2805686936@qq.com2026-05-28T06:45:23Zurn:sha1:f7a69863cbb50a65b9f2d14c4a8ee9085a141b1a[bsp][stm32]:Fix dependencies in ARDUINO2026-05-25T01:33:36ZCYFS2805686936@qq.com2026-05-19T12:37:19Zurn:sha1:0b2e35ab933822da392492468a583481d115315f[bsp][stm32]完善星火1号链接脚本2026-05-24T02:35:56Zguozhanxinguozhanxin@rt-thread.com2026-05-22T06:29:58Zurn:sha1:047ab1eca44e88200de407ddf4347bf0ce175106fix[STM32][SPI]: preload receive-only dummy buffer2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-18T08:02:59Zurn:sha1:3fa50a4b33869050ca8f17e5162b397fddf3e5bf
preload the actual HAL receive buffer with 0xFF for receive-only transfers
rename spi_dma_flag to spi_xfer_flags to match DMA and interrupt flags
clarify SPI async completion and transfer-mode comments
add Doxygen comments for STM32 SPI runtime structures and handlers
fix[STM32][SPI]: ignore benign Tx-only OVR after async completion2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-11T02:44:47Zurn:sha1:bdcaf2ad5633b4bb4231d14189c24a60cc40c0b7feat[STM32][SPI]: add interrupt transfer scaffolding for spi driver2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-05-06T13:02:37Zurn:sha1:415f924c5fb08b03a9b3a5a5ef63a1a7705378b3
introduce interrupt transfer route selection and SPI IRQ visibility macros
unify DMA and INT completion handling with timeout-triggered abort recovery
keep short transfers on polling and use DMA or INT only when eligible
refine STM32 SPI init and IRQ registration paths for mixed transfer backends
feat[STM32][SPI]: refine dma config hierarchy for hard spi2026-05-20T02:42:56Zwdfk-prog1425075683@qq.com2026-04-15T02:53:21Zurn:sha1:e37e3107f4bb18a06f4b922032345a2e1938f893
refine the stm32 hard spi dma configuration hierarchy with shared feature macros
align dma flag usage with rt-device dma flags and gate dma-only fields and paths
make the dma transfer threshold configurable through BSP_SPI_DMA_TRANS_MIN_LEN
[bsp][stm32]:Separate the stm32l1 driver library2026-05-14T03:59:26ZCYFS2805686936@qq.com2026-05-13T02:28:48Zurn:sha1:9a973f4db0b3c0aa9240ab26442245e9eac279b8fix[STM32][I2C]: stabilize async completion and recovery flow for hard i2c2026-05-12T05:36:58Zwdfk-prog1425075683@qq.com2026-05-07T05:36:48Zurn:sha1:ebd3dae49083ac70a1bafae2375f574050ebf3f3
enable I2C error irq when async transfer paths are used fall back to polling when scheduler or interrupt context cannot wait for completion complete the wait path on HAL error callback and abort the transfer on async timeout or error allow INT and DMA mode flags to coexist and keep recovery behavior aligned across STM32 I2C IPs
[format][version]: synchronize bsp version configuration2026-05-08T03:22:12ZCYFS2805686936@qq.com2026-05-08T02:47:41Zurn:sha1:4e46e97c18d4cb53b96b57f373137855b641159f