Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/bsp/xuantie?h=revert-11186-master 2026-01-31T09:44:27Z 2026-01-31T09:44:27Z Bernard Xiong bernard.xiong@gmail.com 2026-01-31T09:44:27Z urn:sha1:743b614875fc33257be47ab53b6c5e040ec27893 * [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue 2025-11-13T10:44:24Z MuChenger ws1516081466@gmail.com 2025-11-13T05:36:10Z urn:sha1:8286196d9ff01fa62987a688bd6c98ec35a83b6d 2025-10-29T05:31:38Z WangShun ws1516081466@gmail.com 2025-10-29T05:31:38Z urn:sha1:e4f014eb96ca35698f2c727cc4339599890f342d 2025-10-23T14:06:51Z kurisaw 2053731441@qq.com 2025-10-23T02:42:47Z urn:sha1:e2aed47b6c0ef75ead36cae04c4e9afd9d8049aa 2025-09-28T08:11:30Z WangShun ws1516081466@gmail.com 2025-09-28T08:11:30Z urn:sha1:cb4a370c71b0e910c2822c23cedfd7dd263a9d10 * [fix] 更新e906的以BSP导入RT-Studio相关文件 2025-09-17T12:03:09Z WangShun ws1516081466@gmail.com 2025-09-17T12:03:09Z urn:sha1:f1bbaf1e25d86fe673cab1b2296a2b7cfac7a4cf [bsp/e906] 添加以BSP方式导入RT-Studio的CDT工程文件 2025-09-03T01:48:22Z Haojin Tang tanghaojin@outlook.com 2025-09-02T14:04:10Z urn:sha1:893ae7d7ba4daecfe4732cb51db8f140dc7211ff 2025-08-23T03:27:59Z Elian Dunmore 75192526+Yaochenger@users.noreply.github.com 2025-08-23T03:27:59Z urn:sha1:bac64cad82a54601cfb4fe0983282db91e5910ac [bsp/xuantie] E902 BSP适配生成CDK工程 [bsp/xuantie] E907 BSP适配生成CDK工程 [bsp/xuantie] C906 BSP适配生成CDK工程 [bsp/xuantie] C907 BSP适配生成CDK工程 [bsp/xuantie] C908 BSP适配生成CDK工程 [bsp/xuantie] C910 BSP适配生成CDK工程 [bsp/xuantie] R908 BSP适配生成CDK工程 [bsp/xuantie] R910 BSP适配生成CDK工程 [bsp/xuantie] R920 BSP适配生成CDK工程 2025-08-19T01:41:30Z Yaochenger 75192526+Yaochenger@users.noreply.github.com 2025-08-19T01:41:30Z urn:sha1:f4e4188197b3033174af0b229399126969a80928 2025-06-27T08:53:50Z Yaochenger 1516081466@qq.com 2025-06-27T07:57:20Z urn:sha1:d62f1e46b893bd2d2e7ada9a7542b1db334d06f5