rt-thread.git/bsp, branch copilot/fix-riscv-none-job-failure

[gd32][build] allow gd32vw553h clean without packages

2026-09-25T05:35:56Z

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

[bsp][ch32v203] add CH32V203C8T6-EVT-R0 support #11827

2026-09-24T08:21:11Z

[bsp/Infineon] Fix PWM macro mismatches left by the CHx_PORTy rename (#11802)

2026-09-21T07:44:01Z

* [bsp/Infineon] Fix PWM macro mismatches left by the CHx_PORTy rename Commit e5382cb733 renamed the PWM table guards in drv_pwm.c to the CHx_PORTy convention but only adapted the psoc6-evk Kconfig, leaving several mismatches behind: - The psoc6-evaluationkit-062S2 slider sample still tested the old flat name BSP_USING_PWM0_PORT0 while the board Kconfig defines BSP_USING_PWM0_CH0_PORT0, so the PWM init was compiled out. - The PORT13 entry was renamed to BSP_USING_PWM0_CH7_PORT13, a macro that no Kconfig defines, and the channel is wrong anyway: PWM0_CH3_PORT13_CONFIG carries .channel = 3, PORT13 sits under the PWM0 CH3 menu, and the slider demo selects CH3 + PORT13. - The PSOC62 template and five psoc6 boards (cy8ckit-062-BLE, cy8ckit-062-WIFI-BT, cy8ckit-062S2-43012, cy8ckit-062s4, cy8cproto-062S3-4343W) still define the old flat names. Fix all of them by migrating the evaluationkit sample to BSP_USING_PWM0_CH0_PORT0 and renaming the PORT13 group to BSP_USING_PWM0_CH3_PORT13 across drv_pwm.c, the PSOC62 template and the five boards' Kconfigs/slider samples, so Kconfig, driver table and samples match again. Note: the sibling guards BSP_USING_PWM0_CH7_PORT2/5/7/9/10/12 are still not generated by these boards' Kconfigs; left untouched for a separate discussion. * style: format code with clang-format [skip ci]

[bsp][gd32] Fix USART TX and RX GPIO initialization

2026-09-21T01:38:05Z

Configure TX as alternate-function push-pull and RX as pull-up input on GD32E50x/F10x/F20x/F30x. Remove the GPIO API alias that incorrectly configured both pins as general-purpose push-pull outputs.

feat[bsp][stm32][h7]: add UART4 RX DMA configuration

2026-09-21T01:36:49Z

Add the missing UART4 RX DMA definitions for STM32H7. UART4 RX DMA uses DMA1 Stream0 with the UART4 RX DMA request. The configuration is enabled when BSP_UART4_RX_USING_DMA is selected.

[bsp][stm32]fix stm32 ld flash oversize #11124

2026-09-17T01:31:36Z

[HC32][BSP] Delete PM_TICKLESS_TIMER_ENABLE_MASK in pm_config.h, modify 'NAME_MAX' to 24 #11798

2026-09-16T09:54:41Z

fix(drv_dma): 修复stm32_dma_type_name函数链接问题

2026-09-16T02:19:06Z

将函数声明从static改为extern，解决跨文件调用时的链接错误，确保DMA、BDMA和GPDMA类型的日志标签能够正确生成。

[bsp][n32] n32hxxx: fix H7xx hard I2C abort and add the missing SDK header

2026-09-16T01:06:34Z

The N32H7xx branch of drv_hard_i2c.c had never been compiled. The file takes its peripheral declarations from board.h, and only n32h497zgl7-evb includes n32h49x_i2c.h, so on H7xx every I2C symbol was undefined and the option could not build at all. Include the peripheral header from the driver itself, the way drv_sdram.c already does. I2C_ABORT_ON_TIMEOUT also degraded to a bare `state = I2C_READY` on H7xx, at the four rt_completion_wait() timeouts in n32_i2c_master_xfer(). The H49x implementation is written against the older IP - I2C_ClrIntPendingBit, I2C_STS2_BUSY, I2C_CTRL1_STOPGEN - none of which exist in the H7xx SDK, so give H7xx its own teardown. It disables the interrupt and DMA request sources, disables the DMA channel that would otherwise stay armed against the caller's buffer, releases the bus and clears the status residue. Only flags with a matching INTCLR bit may be passed to I2C_ClrFlag(), which is a plain "INTCLR |= flag" write; TFC (0x40) and BUSY (0x8000) have none. I2C_Configuration() was called from n32_i2c_init() but defined nowhere in the tree. It is a board hook for pin mux, which is not the driver's job - the H49x path configures no pins either - so drop the call. Verified by building n32h760zil7-stb with BSP_USING_HARD_I2C1 and its TX/RX DMA enabled, which now compiles and links with no warnings, and n32h497zgl7-evb with I2C1/I2C2 DMA enabled, whose image size is unchanged. Neither board routes I2C pins yet, so this is build-verified only, not hardware-verified.

[bsp][n32] n32h497zgl7-evb: add SDRAM port and correct Kconfig defaults

2026-09-16T01:06:34Z

drv_sdram.c includes unconditionally under BSP_USING_SDRAM, and n32h497zgl7-evb had no such header, so the option could not build at all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16 bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at 0x98000000. The timing values are the ones validated on this board in hardware. Three of the Kconfig defaults described a different part: BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16 BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8 BSP_SDRAM_SIZE default 32 -> 8 BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged. Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile and link with no warnings.