rt-thread.git/bsp, branch master

[bsp][spacemit/k1] Enable eight CPUs and add BSP support overview

2026-10-22T09:59:29Z

Increase RT_CPUS_NR from 4 to 8 in the K1 default configuration and regenerate rtconfig.h. Add the SpacemiT K1 entry and peripheral support matrix to the BSP overview. Verified eight-core boot and root filesystem mounting with the RISC-V ticket spinlock fix. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 (#11870)

2026-10-22T07:42:35Z

* [bsp][esp32] adapt C3/C6 to ESP-IDF v6.1 and bump RISC-V toolchain to gcc 15.2 - Adapt ESP32-C3/C6 BSP to ESP-IDF v6.1; bump RISC-V toolchain to gcc 15.2 - C6: re-enable SPI with board-local drv_spi.c; add devices.spi to CI attachconfig; drop shared drv_spi.c spi_command_t hack - C6: fix ADC oneshot multi-channel unit handle and mutex - C3: fix portTRY_ENTER_CRITICAL_SAFE expansion in portmacro.h - Compat with RT-Thread-packages/esp-idf rtt-dev used by CI: map SYSTIMER_* to SYSTIMER_LL_* (C3 and C6 board.c), accept uart_periph.h from hal/ or soc/ - Fix clang-format and cppcheck issues in the compat code Signed-off-by: seteiro Co-Authored-By: Grok * ci: retrigger after esp-idf#18 merged * bsp: ESP: fix C6 ADC for IDF 6.1 (adc_ll bus clock) Replace removed PERIPH_SARADC_MODULE with adc_ll_enable_bus_clock / adc_ll_reset_register when ESP_IDF_VERSION >= 6.0.0. --------- Signed-off-by: seteiro Co-authored-by: Grok

[bsp][spacemit/k1] first version #11132

2026-10-19T10:49:16Z

[bsp][hpmicro] upgrade hpm_sdk to v1.13.0 and add hpm5100evk support

2026-10-17T08:28:33Z

Sync the HPMicro BSPs with hpm_sdk v1.13.0 and add the HPM5100EVK (HPM5151) board. - add the hpm5100evk BSP (board/startup/applications/Kconfig/docs) and register it in .github/ALL_BSP_COMPILE.json, bsp/README.md and the HPMicro READMEs - re-sync the 11 existing boards (board/startup/debug scripts/linker scripts/applications) with hpm_sdk v1.13.0, keeping the RT-Thread specific parts: clock_time based drv_timer, CXX wired into the scons environment, SConscript outputs under build/, named Kconfig choices, rt_hw_us_delay in board_delay_*, board local codec files - sync the shared driver layer with hpm_sdk v1.13.0 (GPTMRv2/PTMR, PUART, soft I2C/SPI and the remaining peripheral driver updates) - select the hpm_sdk v1.13.0 online package (PKG_USING_HPM_SDK_V113) - use -Og instead of -O0 for the debug builds and print floats with the RT-Thread klibc implementation instead of newlib nano - initialize the RT-Thread heap before the SDK console init: the SDK console_init() calls setvbuf(), which allocates through the C library malloc() and tripped RT_ASSERT() in rt_smem_alloc() on the boards built with RT_USING_DEBUG - keep only ram_rtt.ld/flash_rtt.ld per board, align the DLM origin to 4KB on hpm5300evk/hpm5301evklite (the unaligned origin made the linker emit a file backed PT_LOAD for the RAM area, which broke "program rtthread.elf"), and anchor the generated .bin at the flash base address 0x80000000 - sync the hpm6750evk openocd debug scripts with the new style used by the other boards (hpm_common.cfg/hpm_reset.cfg with arp_halt) - keep the upstream synced board/startup/libraries trees of bsp/hpmicro out of the changed-file cppcheck run (same policy as bsp/hpmicro/.clang-format-ignore): the check runs without the hpm_sdk include paths, so it reports ATTR_PLACE_AT and the linker script symbol arithmetic in c_startup() as errors - give the hpmicro boards in the changed-file scons trigger list the RV32 toolchain they need (RISC-V-GCC-RV32) and add the matching installation step to that workflow: the entries used sourcery-arm, which only provides the ARM toolchain, so those legs could not find riscv32-unknown-elf-gcc - keep hpm5100evk's ram_rtt.ld identical to the hpm_sdk v1.13.0 reference: the .fast_ram sections belong in DLM there (the DLM has enough headroom), and that also makes its RAM and flash layouts agree - skip the dependency pre-check when cleaning (scons -c): it runs from DoBuilding() unconditionally, so a clean request with packages/ not fetched yet was aborted with exit code 1 instead of cleaning - make the manual scons trigger workflow runnable: it aborted while still downloading actions because actions/upload-artifact@v3 is deprecated, and scons was not on PATH because ~/.env/env.sh was never sourced. Install tools/requirements.txt and source the Env PATH script in the build step, and use @main action versions, as bsp_buildings.yml does - start the LED demo thread only when rt_thread_create() succeeded Tested: - 12 boards x {ram_debug, ram_release, flash_debug, flash_release}: 48/48 clean builds - flash boot + msh on hpm5100evk, hpm5300evk, hpm5e00evk, hpm6200evk, hpm6300evk, hpm6750evk, hpm6750evk2, hpm6750evkmini, hpm6800evk, hpm6e00evk, hpm6p00evk (list device/timer, ps, free, reset, rt_kprintf float formatting) - re-ran .github/workflows/manual_trigger_scons_except_STM32_all.yml with the matrix reduced to the three hpmicro rows: all three legs build and scons --dist succeeds with no local workarounds

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

[bsp][esp32-c6] address review: chunk SPI xfers to 64B limit, BSP-owned gdma.c, early width check

2026-10-16T03:31:50Z

[bsp][esp32-c6] drop the null SPI configure call

2026-10-16T03:31:50Z

cppcheck follows spi_configure(NULL, NULL) into a dereference. clang-format also wants the macro backslashes left-aligned and a single space around the enum equals.

[bsp][esp32-c6] compile SPI when it is selected

2026-10-16T03:31:50Z

Selecting BSP_USING_SPI on C6 links the IDF SPI master. The default image still leaves SPI off, and the peripheral table stays unsupported.

[bsp][n32] n32hxxx: add the H47x_48x/H49x timer support and cover the BSP with ci-attach

2026-10-15T05:32:50Z

The N32H47x_48x and N32H49x series share drv_tim.c with N32H7xx, but only the H7xx branch was ever implemented, so clock timer, LPTIM, PWM and pulse encoder built to nothing on n32h487zgl7-evb and n32h497zgl7-evb. This adds those branches and gives all three boards a ci-attach entry set that actually compiles what the drivers claim to support. Drivers - drv_tim.c gains the H47x_48x/H49x clock-source and clock-enable branches, the ATIM/GTIM/BTIM instance tables and n32_tim_clock_freq_get(), which reads the real PCLK/HCLK/SYSCLK back from RCC rather than assuming one. ATIMCLKSEL is inverted between the two families and is handled as such. - drv_lptim.c derives its tick from the real LSI value instead of a hard-coded one, unlocks the backup domain before touching RCC, latches the prescaler, and returns -RT_EINVAL rather than clamping a bad rate. - drv_pwm.c and drv_pulse_encoder.c are extended to the H47x_48x/H49x instances; the H7xx encoder's update event is cleared through TIM_EnableUpdateEvt() because that family has no TIM_ConfigUpdateEvt(). - config/{h47x_48x,h49x}/{tim,pwm,pulse_encoder,lptim}_config.h are new and enumerate the instances each series has, for the existing drivers to read. Kconfig Each board defines the timer menus in its own board/Kconfig, so that a board's peripheral options live with the board and the shared driver Kconfig stays series-neutral; libraries/N32_Drivers/drivers/Kconfig is byte-identical to upstream/master. All three copies enforce the mutual exclusion drv_pulse_encoder.c documents (a timer instance enabled for both clock timer and pulse encoder collides at link time on the shared ISR symbol); N32H7xx's menus had none at all and are brought in line. ci-attach 51 entries across the three boards (17/16/18). h487 carries three NAND entries - peripheral.nand, peripheral.nand_16b and peripheral.nand_large - and h497 and h760 carry one each. peripheral.nand_large exists because drv_nand.c picks the row-address cycle count from pages_per_block * block_count: 2 cycles up to 65536 pages, 3 up to 16777216, else 4. Every other NAND entry takes the Kconfig default 64 * 1024 = 65536, which lands exactly on the first boundary, so the >= 3 and >= 4 arms were compiled by nothing at all - it takes a geometry past the 24-bit row width to reach the top rung. The entry pins that geometry to arm them; it is not a claim about the part on the board. Fixes carried in the same series - drv_nand.c emitted its third row-address byte under `== 3`, so a 4-cycle part would set the count to 4 and then match no emitter, dropping the high row-address bytes outright. The three guards are now >= 3 with the >= 4 byte added. row_addr is uint32_t at all three sites. - timer_ctrl() wrote the prescaler straight to a 16-bit PSC field. TIM_ConfigPrescaler() neither masks nor validates, so any freq below timer_clock/65537 was truncated and the timer ran at an unrelated rate while timer->freq still recorded the requested one. That window is reachable: both boards clock timers at 240 MHz, so the honest floor is ~3662 Hz while tim_config.h sets minfreq = 3000 and only [minfreq, maxfreq] is checked - 3000 Hz lands in PSC as 14463, about 16.6 kHz. Division by zero and any prescaler above 0xFFFF now return -RT_EINVAL. The H7xx branch had the identical truncation, so the same two guards are applied there too. - n32_tim_enable_clock() closed each new branch with RT_ASSERT(RT_TRUE). With RT_DEBUGING_ASSERT on, RT_ASSERT() expands to `if (!(EX)) rt_assert_handler(...)`, so that guard could never fire: a timer matching none of the branch's instances enabled no clock at all and the caller went on to touch an unclocked peripheral's registers. All three branches are now RT_FALSE. The H7xx guard cannot fire today - every instance its config header can hand out is already in that branch's ladder - so fixing it arms the guard against a future instance added to the table but not the ladder, rather than changing any existing configuration. - h497's sdram entry asked for BSP_SDRAM_SIZE=32 while sdram_port.h documents the part as 8 MB and board/Kconfig declares `range 8 256` with `default 8`; the 32 came from h760, whose own default happens to be 32. - drv_hard_i2c.c had no init path at all for H47x_48x/H49x, leaving those series with an unconfigured controller; the SCL rate now travels in the config struct instead of being assumed. - drv_qspi.c and drv_spi.c indexed buffers longer than 65535 bytes with 16-bit counters, which wraps at exactly 65536. - n32eth_cfg.h is added because the H7xx and H49x SDKs' eth.h include it but no package in the tree ships it. It probes for the series headers because the SDK includes it before rtconfig.h can define SOC_SERIES_*, with a part-macro fallback for ARM Compiler 5, which has no __has_include() and is what every Keil project in this BSP uses. - n32h487zgl7-evb now builds with its real 8 MHz crystal; left at the header's 16 MHz default, RCC_GetClocksFreqValue() reports every clock at twice its value and the timer prescalers come out twice too large. - n32h760zil7-stb's timer menus had no mutual exclusion at all, so a timer instance could be enabled as both a clock timer and a pulse encoder; 24 ISR symbols are defined by both drivers under those two guards, so only the linker would have caught it. Its 14 PWM menus and its 14 encoder entries now carry the same guard as the two new boards', using the PWMn == PULSE_ENCODERN == instance n mapping that config/h7xx's pulse_encoder_config.h establishes. On the PWM side that guard is a resource guard, not a link one: drv_pwm.c defines no ISRs. - the same board's LPTIM menu selected RT_USING_LPTIMER, which is not declared anywhere in the tree. A select of an undeclared symbol is an implicit symbol and raises no diagnostic, so the line had never done anything; it is dropped, as the two new menus already do. Three stm32 boards still carry it and are left alone. The H49x LPTIM EXTI lines needed the user manual rather than the SDK to settle, and the manual sides with the driver: N32H49x maps EXTI line 21 to the LPTIM1 wakeup event and line 22 to LPTIM2, which is what n32_lptim_get_exti_line() returns. The headers disagree only because n32h49x_exti.h's EXTI_LINE16..24 block is a verbatim copy of n32h47x_48x_exti.h's - that one carries on past line 24 and names 25/26 as the LPTIM events with 21/22 as COMP1/COMP4 - while the H49x series has no comparator in its SDK at all, so its copy of that text is stale. The driver states the reasoning in a comment rather than the bare value. The H49x timer clock-source bits needed the user manual rather than the SDK to settle. For GTIM8/9/10 (RCC_CFG2 bit 27) h49x names the cleared case RCC_GTIM_CLKSRC_SYSCLKDIV where h47x_48x names it RCC_GTIM_CLKSRC_PCLK, and the manual sides with the driver's arithmetic: bit 27 selects SYSCLK, or SYSCLK/(APB2 prescaler / 2) when that prescaler is engaged - the same rule the driver writes from the HCLK side as PCLK2 doubled whenever PCLK2 is below HCLK. Both boards hold AHBPRES at RCC_SYSCLK_DIV1, so HCLK and SYSCLK are the same 240 MHz and either spelling gives the same number. The driver tests the raw bit and not either family's constant, so the naming difference never reaches the code. The same chapter confirms bit 28's inversion, which the ATIM branches already follow. Verified: all three boards build from scratch under --strict (gcc -Werror) with zero diagnostics; all 51 ci-attach entries build clean; the three series were rebuilt after the assert fix, each through the --attach path that compiles its branch (devices.timer on all three boards - h760's default leaves BSP_USING_CLOCK_TIMER off, so drv_tim.c is not compiled by it at all), rebuilt again after the Kconfig guards, whose effect was checked by loading the tree with kconfiglib and confirming that clock-timer ATIM1 with pulse encoder1 goes from satisfiable to unsatisfiable while a non-colliding pair is left alone); the NAND row-address arms were confirmed compiled by injecting #error markers and rebuilding through the real --attach path; each board's committed .config and rtconfig.h reproduce byte-for-byte from a fresh defconfig; and the CI clang-format gate reports 0 files / 0 lines.

Change the main thread stack size to 4096

2026-10-14T01:44:44Z